TDMA Digital Radio Processor
CMX7161
64-pin
Q1/L9
Pin
Description
Pin No.
Name
Type
Internally generated bias voltage of approximately AVDD/2. If
VBIAS is powersaved this pin will be connected via a high
impedance to AVDD. This pin must be decoupled to AVSS by
a capacitor mounted close to the device pins.
27
VBIAS
OP
28
29
30
31
32
33
34
35
36
IINPUTP
IP
IP
~
Differential inputs for I channel signals; ‘P’ is positive, ‘N’ is
negative. Together these are referred to as the I Input.
IINPUTN
ADCREF
QINPUTP
QINPUTN
AUXADC1
AUXADC2
AUXADC3
AUXADC4
ADC reference voltage; connect to AVSS
IP
IP
IP
IP
IP
IP
Differential inputs for Q channel signals; ‘P’ is positive, ‘N’ is
negative. Together these are referred to as the Q Input.
Auxiliary ADC input 1
Auxiliary ADC input 2
Auxiliary ADC input 3
Auxiliary ADC input 4
Positive 3.3V supply rail for the analogue on-chip circuit.
Levels and thresholds within the device are proportional to
this voltage. This pin should be decoupled to AVSS by
capacitors mounted close to the device pins.
37
AVDD
PWR
Negative supply rail (ground) for the analogue on-chip
circuits
38
AVSS
PWR
39
40
41
42
43
AUXDAC1
AUXDAC2
AUXDAC3
AUXDAC4
DVSS
OP
Auxiliary DAC output 1 (Optionally the RAMDAC output)
Auxiliary DAC output 2
OP
OP
Auxiliary DAC output 3
OP
Auxiliary DAC output 4
PWR
Negative supply rail (ground) for the digital on-chip circuits
Internally generated digital core voltage of approximately
1.8V. This pin should be decoupled to DVSS by capacitors
mounted close to the device pins
44
45
DVCORE
DVDD
PWR
PWR
3.3V positive supply rail for the digital on-chip circuits. This
pin should be decoupled to DVSS by capacitors mounted
close to the supply pins.
46
47
48
49
50
51
52
53
NC
NC
PWR
PWR
NC
IP
Do not connect
DVSS
Negative supply rail (ground) for the digital on-chip circuits
Negative supply rail (ground) for the digital on-chip circuits
Do not connect
DVSS
NC
SYSCLKIN
SYSCLK1
SYSCLK2
SCLK
Input from the external system clock source
Synthesised digital clock output 1
OP
OP
IP
Synthesised digital clock output 2
C-BUS serial clock input from the µC
2013 CML Microsystems Plc
Page 9
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
