TDMA Digital Radio Processor
CMX7161
64-pin
Q1/L9
Pin
Description
Pin No.
Name
RDATA
Type
3-state C-BUS serial data output to the µC. This output is
high impedance when not sending data to the µC.
54
TS OP
55
56
CDATA
CSN
IP
IP
C-BUS serial data input from the µC
C-BUS chip select input from the µC
‘wire-Orable’ output for connection to the Interrupt Request
input of the µC. This output is pulled down to DVSS when
active and is high impedance when inactive. An external
pull-up resistor is required.
57
58
IRQN
OP
Internally generated digital core voltage of approximately
1.8V. This pin should be decoupled to DVSS by capacitors
mounted close to the device pins
DVCORE
PWR
59
60
61
62
63
64
MOSI
OP
OP
IP
SPI: Master Out Slave In
SSOUT1
MISO
SPI: Slave Select Out 1
SPI: Master In Slave Out
SSOUT0
CLK
OP
OP
BI
SPI: Slave Select Out 0
SPI: Serial Clock
GPIOA
General Purpose I/O (Used as Rx Enable on DE9943)
On this device, the central metal pad (which is exposed on the Q1
package only) may be electrically unconnected or,
alternatively, may be connected to Analogue ground (AVss).
EXPOSED
METAL PAD
SUBSTRATE
~
No other electrical connection is permitted.
Notes: IP
=
Input (+ PU/PD = internal pull-up / pull-down resistor of approximately 75kΩ)
OP
BI
TS OP
PWR
NC
=
=
=
=
=
Output
Bidirectional
3-state Output
Power Connection
No Connection - should NOT be connected to any signal
3.1
Signal Definitions
Table 1 Definition of Power Supply and Reference Voltages
Signal
Name
Pins
Usage
Power supply for analogue circuits
Power supply for digital circuits
Power supply for core logic, derived from DV by on-chip regulator
AV
DV
AVDD
DVDD
DVCORE
VBIAS
AVSS,
SUBSTRATE
DD
DD
DVCORE
DD
V
BIAS
Internal analogue reference level, derived from AV
Ground for all analogue circuits
DD
AV
SS
SS
DV
DVSS
Ground for all digital circuits
2013 CML Microsystems Plc
Page 10
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
