TDMA Digital Radio Processor
CMX7161
CONTENTS
Section
Page
1
2
3
Brief Description...................................................................................................................... 2
Block Diagrams........................................................................................................................ 6
Signal List................................................................................................................................. 8
3.1
Signal Definitions........................................................................................................ 10
4
5
PCB Layout Guidelines and Power Supply Decoupling.................................................... 11
External Components............................................................................................................ 12
5.1
5.2
5.3
5.4
System Clock Interface............................................................................................... 12
C-BUS Interface.......................................................................................................... 12
2-point Output Reconstruction Filter........................................................................... 12
GPIO Pins................................................................................................................... 13
6
7
General Description............................................................................................................... 14
Detailed Descriptions............................................................................................................ 15
7.1
7.2
7.3
External Oscillator Frequency..................................................................................... 15
Radio Interface ........................................................................................................... 15
Host Interface ............................................................................................................. 15
7.3.1 C-BUS Operation ................................................................................................. 15
7.3.2 C-BUS Timing ...................................................................................................... 16
Function Image™ Loading.......................................................................................... 18
7.4.1 FI Loading from Host Controller........................................................................... 18
7.4.2 FI Loading from Serial Memory............................................................................ 20
Device Control ............................................................................................................ 21
7.5.1 Device Control Overview...................................................................................... 21
7.5.2 Device Configuration (Programming Register) .................................................... 21
7.5.3 Data Transfer ....................................................................................................... 21
7.5.4 Interrupt Operation............................................................................................... 21
7.5.5 Signal Control....................................................................................................... 22
Modulation Format...................................................................................................... 22
7.6.1 Typical Transmit Performance............................................................................. 22
Slot Structure and Frame Synchronisation................................................................. 23
Operating Modes ........................................................................................................ 25
7.8.1 Sleep Mode (0000)............................................................................................... 26
7.8.2 Tx Set-up Mode (1001) ........................................................................................ 26
7.8.3 Tx PRBS Mode (1010)......................................................................................... 26
7.8.4 Tx Data Mode (1011) ........................................................................................... 26
7.8.5 Rx Set-up Mode (0001)........................................................................................ 26
7.8.6 Rx Eye Mode (0010) ............................................................................................ 26
7.8.7 Rx Data Mode (0011)........................................................................................... 26
7.8.8 Slotted Data Mode (1111).................................................................................... 27
Signal Level Optimisation ........................................................................................... 27
7.9.1 Transmit Path Levels ........................................................................................... 27
7.9.2 Receive Path Levels............................................................................................. 27
7.4
7.5
7.6
7.7
7.8
7.9
7.10
External Interfaces...................................................................................................... 28
7.10.1 GPIO Pin Operation ............................................................................................. 28
2013 CML Microsystems Plc
Page 3
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
