AX.25 Modem
CMX7031/CMX7041
7.13.1 Interrupt Operation
The CMX7031/CMX7041 will issue an interrupt on the IRQN line when the IRQ bit (bit 15) of the Status
register and the IRQ Mask bit (bit 15) are both set to 1. The IRQ bit is set when the state of the interrupt
flag bits in the Status register change from a 0 to 1 and the corresponding mask bit(s) in the Interrupt
Mask register is (are) set. Enabling an interrupt by setting a mask bit (01) after the corresponding Status
register bit has already been set to 1 will also cause the IRQ bit to be set.
All interrupt flag bits in the Status register, except the Programming Flag (bit 0) and the RF Channel Status
Flag (bit 1), are cleared and the interrupt request is cleared following the command/address phase of a C-
BUS read of the Status register. The Programming Flag bit is set to 1 only when it is permissible to write a
new word to the Programming register.
See:
o
o
Status – $C6 read
Interrupt Mask - $CE write
7.13.2 General Notes
In normal operation, the most significant registers are:
o
o
o
o
Mode Control – $C1 write
Status – $C6 read
Input Gain and Routing - $B1 write
Output Level – $C2 write
Setting the Mode register to either Rx or Tx will automatically increase the internal clock speed to its
operational speed, whilst setting the Mode register to Idle will automatically return the internal clock to a
lower (powersaving) speed. To access the Program Blocks (through the Programming register, $C8) the
device MUST be in Idle mode.
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