AX.25 Modem
CMX7031/CMX7041
7.10.1 Main Clock Operation
A PLL is used to create the Main Clock (nominally 49.512MHz) for the internal sections of the
CMX7031/CMX7041. At the same time, other internal clocks are generated by division of either the XTAL
Reference Clock or the Main Clock. These internal clocks are used for determining the sample rates and
conversion times of A-to-D and D-to-A converters, running a General Purpose Timer, the signal
processing block and the RF Synthesisers.
The CMX7031/CMX7041 defaults to the settings appropriate for a 19.2Hz oscillator, with 12.4MHz
selection available by setting $C3 appropriately.
See:
o
Clock Control - $C3 write
7.10.2 System Clock Operation
Two System Clock outputs, SYSCLK1 and SYSCLK2, are available to drive additional circuits, as required.
These are phase locked loop (PLL) clocks that can be programmed via the System Clock registers with
suitable values chosen by the user. The System Clock PLL Configure registers ($AB and $AD) control the
values of the VCO Output divider and Main Divide registers, while the System Clock Ref. Configure
registers ($AC and $AE) control the values of the Reference Divider and signal routing configurations. The
PLLs are designed for a reference frequency of 96kHz. If not required, these clocks can be independently
powersaved. The clock generation scheme is shown in the block diagram of Figure 18. Note that at power-
on, these pins provide, by default:
CMX7031: XTAL clk
CMX7041: no signal (off)
See:
o
o
SYSCLK 1 and 2 PLL data - $AB, $AD write
SYSCLK1 and 2 REF - $AC and $AE write
7.11 GPIO
Four pins on the device are provided for GPIO purposes. GPIO 1 and 2 are driven by the
CMX7031/CMX7041 to follow the state of the Rx and Tx Mode bits in the Mode register, $C1:
Table 7 GPIO States
$C1 Mode
Idle
Rx
Tx
reserved
b1
0
0
1
1
b0
0
1
0
1
TxENA
RxENA
1
1
0
1
1
0
1
1
The timing of the TxENA signal is defined by the Tx Sequencer values. At power-on, their default state is
high impedance input. GPIO A and B may be driven or read under host control.
See:
o
GPIO Control - $A7 16-bit write
7.12 Signal Level Optimisation
The internal signal processing of the CMX7031/CMX7041 will operate with wide dynamic range and low
distortion only if the signal level at all stages in the signal processing chain is kept within the recommended
limits. For a device working from a 3.3V ±10% supply, the maximum signal level which can be
accommodated without distortion is [(3.3 x 90%) – (2 x 0.3V)] Volts pk-pk = 838mV rms, assuming a sine
wave signal. Compared to the reference level of 308mV rms, this is a signal of +8.69dB. This should not
be exceeded at any stage. The various level adjustment facilities are shown in Figure 19.
2013 CML Microsystems Plc
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