EP9315
Enhanced Universal Platform SOC Processor
Static Memory Burst Read Cycle
Parameter
Symbol
tADd1
tADd2
tADd3
tADh
Min
Typ
Max
Unit
tHCLK × (WST1 + 1)
CSn assert to Address 1 transition time
Address assert time
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHCLK × (WST2 + 1)
-
-
tHCLK × (WST1 + 2)
AD transition to CSn deassert time
AD hold from CSn deassert time
CSn to RDn delay time
-
tHCLK
-
-
-
-
-
-
-
-
tRDd
-
3
1
-
tDQMd
tDAs1
tDAs2
tDAh1
tDAh2
CSn to DQMn assert delay time
DA setup to AD transition time
DA setup to CSn deassert time
DA hold from AD transition time
DA hold from RDn deassert time
-
15
tHCLK + 12
-
0
0
-
-
Note: These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
tADs
tADh
tADd1
tADd2
tADd2
tADd3
AD
CSn
WRn
RDn
tRDd
tDQMd
DQMn
tDAh1
tDAh1
tDAh1
tDAh2
DA
tDAs1
tDAs1
tDAs1
tDAs2
WAIT
Figure 12. Static Memory Burst Read Cycle Timing Measurement
DS638PP4
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