EP9315
Enhanced Universal Platform SOC Processor
Static Memory Turnaround Cycle
Parameter
Symbol
Min
Typ
Max
Unit
tBTcyc
tHCLK × (IDCY+1)
CSnX deassert to CSnY assert time
-
-
ns
Notes: 1. X and Y represent any two chip select numbers.
2. IDCY occurs on read-to-write and write-to-read.
3. IDCY is honored when going from a asynchronous device (CSx) to a synchronous device (/SDCSy).
tBTcyc
AD
CSnX
CSnY
WRn
RDn
DQMn
DA
WAIT
Figure 16. Static Memory Turnaround Cycle Timing Measurement
DS638PP4
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