CS8900A
Crystal LAN™ ISA Ethernet Controller
5.7 Transmit Operation
5.7.2.1 Configuring the Physical Interface
Configuring the physical interface consists of de-
termining which Ethernet interface should be ac-
tive (10BASE-T or AUI), and enabling the transmit
logic for serial transmission. Configuring the Phys-
ical Interface is accomplished via the LineCTL reg-
ister (Register 13) and is described in Table 30.
5.7.1 Overview
Packet transmission occurs in two phases. In the
first phase, the host moves the Ethernet frame into
the CS8900A’s buffer memory. The first phase be-
gins with the host issuing a Transmit Command.
This informs the CS8900A that a frame is to be
transmitted and tells the chip when (i.e. after 5,
381, or 1021 bytes have been transferred or after
the full frame has been transferred to the CS8900A)
and how the frame should be sent (i.e. with or with-
out CRC, with or without pad bits, etc.). The host
follows the Transmit Command with the Transmit
Length, indicating how much buffer space is re-
quired. When buffer space is available, the host
writes the Ethernet frame into the CS8900A’s inter-
nal memory, using either Memory or I/O space.
Register 13, LineCTL
Bit
7
Bit Name
SerTxON
AUIonly
Operation
When set, transmission enabled.
8
When set, AUI selected (takes
precedenceoverAutoAUI/10BT).
When clear, 10BASE-T selected.
9
AutoAUI/10BT When set, automatic interface
selection enabled.
B
Mod
BackoffE
When set, the modified backoff
algorithm is used. When clear,
the standard backoff algorithm is
used.
D
2-part
DefDis
When set, two-part deferral is
disabled.
In the second phase of transmission, the CS8900A
converts the frame into an Ethernet packet then
transmits it onto the network. The second phase be-
gins with the CS8900A transmitting the preamble
Table 30. Physical Interface Configuration
Note that the CS8900A transmits in 10BASE-T
and Start-of-Frame delimiter as soon as the proper mode when no link pulses are being received only
number of bytes has been transferred into its trans- if bit DisableLT is set in register Test Control (Reg-
mit buffer (5, 381, 1021 bytes or full frame, de- ister 19).
pending on configuration). The preamble and Start-
5.7.2.2 Selecting which Events Cause Interrupts
of-Frame delimiter are followed by the data trans-
The TxCFG register (Register 7) and the BufCFG
ferred into the on-chip buffer by the host (Destina-
register (Register B) are used to determine which
tion Address, Source Address, Length field and
transmit events will cause interrupts to the host pro-
LLC data). If the frame is less than 64 bytes, in-
cessor. Tables 31 and 32 describe the interrupt en-
able (iE) bits in these registers.
cluding CRC, the CS8900A adds pad bits if config-
ured to do so. Finally, the CS8900A appends the
proper 32-bit CRC value.
5.7.3 Changing the Configuration
When the host configures these registers it does not
need to change them for subsequent packet trans-
missions. If the host does choose to change the Tx-
CFG or BufCFG registers, it may do so at any time.
The effects of the change are noticed immediately.
That is, any changes in the Interrupt Enable (iE)
bits may affect the packet currently being transmit-
ted.
5.7.2 Transmit Configuration
After each reset, the CS8900A must be configured
for transmit operation. This can be done automati-
cally using an attached EEPROM, or by writing
configuration commands to the CS8900A’s internal
registers (see Section 3.4 on page 21). The items
that must be configured include which physical in-
terface to use and which transmit events cause in-
terrupts.
CIRRUS LOGIC PRODUCT DATA SHEET
DS271PP3
99
CIRRUS [ CIRRUS LOGIC ]
