欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS8900A-IQ3 参数 Datasheet PDF下载

CS8900A-IQ3图片预览
型号: CS8900A-IQ3
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
 浏览型号CS8900A-IQ3的Datasheet PDF文件第93页浏览型号CS8900A-IQ3的Datasheet PDF文件第94页浏览型号CS8900A-IQ3的Datasheet PDF文件第95页浏览型号CS8900A-IQ3的Datasheet PDF文件第96页浏览型号CS8900A-IQ3的Datasheet PDF文件第98页浏览型号CS8900A-IQ3的Datasheet PDF文件第99页浏览型号CS8900A-IQ3的Datasheet PDF文件第100页浏览型号CS8900A-IQ3的Datasheet PDF文件第101页  
CS8900A  
Crystal LAN™ ISA Ethernet Controller  
Enter Example Here  
Entering this example, the receive buffer is empty and the  
DMA Frame Count (PacketPage base + 0028h) is zero.  
F
F
r
a
a
m
e
1
2
Frame 1 received and completely stored in on-chip RAM.  
Frame 2 received and completely stored in on-chip RAM.  
r
m
e
Time  
At this point, the CS8900A does not have sufficient buffer  
space for another complete large frame (1518 bytes).  
F
r
a
m
e
3
Frame 3 starts to be received and passes the DA filter.  
This activates Auto-Switch DMA.  
Frame 1 is placed in host memory via DMA freeing  
space for the incoming Frame 3. The CS8900A updates  
the DMA Frame Count, DMA Start of Frame and DMA  
Byte Count registers. It then sets the RxDMA DMAFrame  
bit and generates an interrupt.  
Receive DMA used  
during this time.  
Frame 2 is placed in host memory via DMA and the  
CS8900A updates the DMA registers.  
The host responds to the RxDMAFrame interrupt, and  
reads the Frame Count register, which is cleared when  
read. Since there are no receive interrupts pending, the  
CS8900A exits DMA (assumes Frame 3 is still coming in).  
Frame 3 is completely buffered in on-chip RAM, and  
awaits processing by the host.  
Exit Example  
Figure 27. Example of Auto-Switch DMA  
CIRRUS LOGIC PRODUCT DATA SHEET  
DS271PP3  
97  
 复制成功!