CS8900A
Crystal LAN™ ISA Ethernet Controller
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all packets received are of legal length with val- 5.6.5 Example of StreamTransfer
id CRC;
Figure 28 shows how four back-to-back frames,
followed by five back-to-back frames, would be re-
ceived without StreamTransfer. Figure 29 shows
how the same sequence of frames would be re-
ceived with StreamTransfer.
each packet follows its predecessor by less than
52 ms; and,
the DA of each packet passes the DA filter.
If any of these conditions are not met, the CS8900A
exits StreamTransfer by generating RxOK and
RxDMA interrupts. The CS8900A then returns to
either Memory, I/O, or DMA mode, depending on
configuration.
5.6.6 Receive DMA Summary
Table 29 summarize the Receive DMA configura-
tion options supported by the CS8900A.
RxDMAonly AutoRxDMAiE
(Register 3, (Register 3,
RxDMAiE
(Register B, (Register 3,
RxOKiE
CS8900A Configuration
RxCFG,Bit 9) RxCFG, Bit A) BufCFG, Bit 7) RxCFG, Bit 8)
1
1
0
0
0
NA
NA
1
0
NA
NA
0
Receive DMA used for all receive frames, without
interrupts.
1
Receive DMA used for all receive frames, with
BufEvent interrupts.
0
Auto-Switch DMA used if necessary, without inter-
rupts.
1
1
1
Auto-Switch DMA used if necessary, with RxEvent
and BufEvent interrupts possible.
0
NA
NA
Memory or I/O Mode only.
Table 29. Receive DMA Configuration Options
4 Back-to-Back Frames
T > 52 us
5 Back-to-Back Frames
Interrupt
Request
9 Interrupts for 9 "Good" Packets
Time
Figure 28. Receive Example Without Stream Transfer
4 Back-to-Back Frames
T > 52 us
5 Back-to-Back Frames
Interrupt
Request
2 Interrupts for 9 "Good" Packets
Time
Figure 29. Receive DMA Configuration Options
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