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CS8900A-IQ3 参数 Datasheet PDF下载

CS8900A-IQ3图片预览
型号: CS8900A-IQ3
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
all packets received are of legal length with val- 5.6.5 Example of StreamTransfer  
id CRC;  
Figure 28 shows how four back-to-back frames,  
followed by five back-to-back frames, would be re-  
ceived without StreamTransfer. Figure 29 shows  
how the same sequence of frames would be re-  
ceived with StreamTransfer.  
each packet follows its predecessor by less than  
52 ms; and,  
the DA of each packet passes the DA filter.  
If any of these conditions are not met, the CS8900A  
exits StreamTransfer by generating RxOK and  
RxDMA interrupts. The CS8900A then returns to  
either Memory, I/O, or DMA mode, depending on  
configuration.  
5.6.6 Receive DMA Summary  
Table 29 summarize the Receive DMA configura-  
tion options supported by the CS8900A.  
RxDMAonly AutoRxDMAiE  
(Register 3, (Register 3,  
RxDMAiE  
(Register B, (Register 3,  
RxOKiE  
CS8900A Configuration  
RxCFG,Bit 9) RxCFG, Bit A) BufCFG, Bit 7) RxCFG, Bit 8)  
1
1
0
0
0
NA  
NA  
1
0
NA  
NA  
0
Receive DMA used for all receive frames, without  
interrupts.  
1
Receive DMA used for all receive frames, with  
BufEvent interrupts.  
0
Auto-Switch DMA used if necessary, without inter-  
rupts.  
1
1
1
Auto-Switch DMA used if necessary, with RxEvent  
and BufEvent interrupts possible.  
0
NA  
NA  
Memory or I/O Mode only.  
Table 29. Receive DMA Configuration Options  
4 Back-to-Back Frames  
T > 52 us  
5 Back-to-Back Frames  
Interrupt  
Request  
9 Interrupts for 9 "Good" Packets  
Time  
Figure 28. Receive Example Without Stream Transfer  
4 Back-to-Back Frames  
T > 52 us  
5 Back-to-Back Frames  
Interrupt  
Request  
2 Interrupts for 9 "Good" Packets  
Time  
Figure 29. Receive DMA Configuration Options  
CIRRUS LOGIC PRODUCT DATA SHEET  
98  
DS271PP3  
 
 
 
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