CS8900A
Crystal LAN™ ISA Ethernet Controller
the correct location by writing 0138h to the
PacketPage Pointer Port (I/O base + 000Ah), it
than can read the BusST register from the Pack-
etPage Data Port (I/O base + 000Ch).After
reading the register, the Rdy4TxNOW bit is
checked. If the bit is set, the frame can be writ-
ten to CS8900A memory. If Rdy4TxNOW is
clear, the host will have to wait for the
CS8900A buffer memory to become available
at which time the host will be interrupted. On
interrupt, the host enters the interrupt service
routine and reads ISQ register (Memory base +
0120h in memory mode and I/O base + 0008h
in I/O) and checks the Rdy4Tx bit (bit 8). If
Rdy4Tx is clear then the CS8900A waits for the
next interrupt. If Rdy4Tx is set, then the
CS8900A is ready to accept the frame.
Figure 30 provides a diagram of error free trans-
mission without collision.
5.7.10 Committing Buffer Space to a Transmit
Frame
When the host issues a transmit request, the
CS8900A checks the length of the transmit frame
to see if there is sufficient on-chip buffer space. If
there is, the CS8900A sets the Rdy4TxNOW bit. If
not, and the Rdy4TxiE bit is set, the CS8900A
waits for buffer space to free up and then sets the
Rdy4Tx bit. If Rdy4TxiE is not set, the CS8900A
sets the Rdy4TxNOW bit when space becomes
available.
Even though transmit buffer space may be avail-
able, the CS8900A does not commit buffer space to
a transmit frame until all of the following are true:
1) The host must issues a Transmit Request;
4) When the CS8900A is ready to accept the
frame, the host transfers the entire frame from
host memory to CS8900A memory using REP
instruction (REP MOVS to memory base +
0A00h in memory mode, and REP OUT to Re-
ceive/Transmit Data Port (I/O base + 0000h) in
I/O mode).
2) The Transmit Request must be successful; and,
3) Either the host reads that the Rdy4TxNOW bit
(Register 18, BusST, Bit 8) is set, or the host
reads that the Rdy4Tx bit (Register C, BufE-
vent, bit 8) is set.
If the CS8900A commits buffer space to a particu-
lar transmit frame, it will not allow subsequent
frames to be written to that buffer space as long as
the transmit frame is committed.
5.7.8 Completing Transmission
When the CS8900A successfully completes trans-
mitting a frame, it sets the TxOK bit (Register 8,
TxEvent, Bit 8). If the TxOKiE bit (Register 7, Tx-
CFG, bit 8) is set, the CS8900A generates a corre-
sponding interrupt.
After buffer space is committed, the frame is sub-
sequently transmitted unless any of the following
occur:
5.7.9 Rdy4TxNOW vs. Rdy4Tx
1) The host completely writes the frame data, but
transmission failed on the Ethernet line. There
are three such failures, and these are indicated
by three transmit error bits in the TxEvent reg-
ister (Register 8): 16coll, Jabber, or Out-of-
Window.
The Rdy4TxNOW bit (Register 18, BusST, bit 8) is
used to tell the host that the CS8900A is ready to
accept a frame for transmission. This bit is used
during the Transmit Request process or after the
Transmit Request process to signal the host that
space has become available when interrupts are not
being used (i.e. the Rdy4TxiE bit (Register B,
BufCFG, Bit 8) is not set). Also, the Rdy4Tx bit is
used with interrupts and requires the Rdy4TxiE bit
be set.
Or:
2) The host aborts the transmission by setting the
Force (Register 9, TxCMD, bit 8) bit. In this
case, the committed transmit frame, as well as
CIRRUS LOGIC PRODUCT DATA SHEET
DS271PP3
103
CIRRUS [ CIRRUS LOGIC ]
