CS5460A
5. REGISTER DESCRIPTION
Current
Channel
Signed Output Registers (4 × 24)
(I, V, P, E)
DC Offset Register (1 × 24)
AC/DC Gain Register (1 × 24)
AC/DC Gain Register (1 × 24)
Cycle-Counter Register (1 × 24)
AC Offset Register (1 x 24)
AC Offset Register (1 x 24)
Power Offset Register (1 x 24)
Voltage
Channel
DC Offset Register (1 × 24)
Pulse-Rate Register (1 × 24)
Unsigned Output Registers (2 × 24)
(I
, V )
RMS RMS
Receive Buffer
SDI
CS
Serial Interface
Transmit Buffer
24-Bit
SDO
Timebase Cal. Register (1 x 24)
Status Register (1 × 24)
Mask Register (1 × 24)
Control Register (1 x 24)
Command Word
State Machine
SCLK
INT
Configuration Register (1 × 24)
Figure 21. CS5460A Register Diagram
Note: 1. ** “default” => bit status after software or hardware reset
2. Note that all registers can be read from, and written to.
5.1 Configuration Register
Address: 0
23
22
21
20
19
18
17
16
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Gi
15
14
13
12
11
10
9
8
EWA
Res
Res
SI1
SI0
EOD
DL1
DL0
7
6
5
4
3
2
1
0
RS
VHPF
IHPF
iCPU
K3
K2
K1
K0
Default** = 0x000001
K[3:0]
Clock divider. A 4 bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero).
iCPU
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = normal operation (default)
1 = minimize noise when CPUCLK is driving rising edge logic
IHPF
Control the use of the High Pass Filter on the Current Channel.
0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used.
(default)
1 = High-pass filter is enabled.
VHPF
Control the use of the High Pass Filter on the voltage Channel.
0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used.
(default)
1 = High-pass filter enabled
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CIRRUS [ CIRRUS LOGIC ]
