CS5460A
4.1.7 Register Read/Write
B7
B6
B5
B4
B3
B2
B1
B0
0
W/R
RA4
RA3
RA2
RA1
RA0
0
This command informs the state machine that a register access is required. On reads the addressed register is load-
ed into the output buffer and clocked out by SCLK. On writes the data is clocked into the input buffer and transferred
th
to the addressed register on the 24 SCLK.
W/R
Write/Read control
0 = Read register
1 = Write register
RA[4:0]
Register address bits. Binary encoded 0 to 31. All registers are 24 bits in length.
Address
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
.
Abbreviation
Config
IDCoff
Ign
VDCoff
Vgn
Cycle Count
Pulse-Rate
Name/Description
Configuration Register.
Current Channel DC Offset Register.
Current Channel Gain Register.
Voltage Channel DC Offset Register.
Voltage Channel Gain Register.
Number of A/D cycles per computation cycle.
Used to set the energy-to-pulse ratio on EOUT (and EDIR).
Instantaneous Current Register (most recent current sample).
Instantaneous Voltage Register (most recent voltage sample).
Instantaneous Power Register (most recent power sample).
Energy Register (accumulated over latest computation cycle).
RMS Current Register (computed over latest computation cycle).
RMS Voltage Register (computed over latest computation cycle).
Timebase Calibration Register.
Power Offset Register.
I
V
P
E
I
RMS
V
RMS
TBC
Poff
Status
IACoff
VACoff
Res
.
Status Register.
Current Channel AC Offset Register.
Voltage Channel AC Offset Register.
Reserved †
.
.
.
.
10111
11000
11001
11010
11011
11100
11101
.
Res
Res
Test
Mask
Res
Ctrl
Res
.
Reserved †
Reserved †
Reserved †
Mask Register.
Reserved †
Control Register.
Reserved †
.
.
.
.
11111
Res
Reserved †
† These registers are for Internal Use only and should not be written to.
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