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CS5460A-BS 参数 Datasheet PDF下载

CS5460A-BS图片预览
型号: CS5460A-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 单相双向功率/电能IC [Single Phase Bi-Directional Power/Energy IC]
分类和应用:
文件页数/大小: 54 页 / 879 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5460A  
slow rise times and/or noisy control signals. (It is  
not uncommon to experience temporary periods of  
abnormally high noise and/or slow, gradual resto-  
ration of power, during/after a power “black-out” or  
power “brown-out” event.) Once the RESET pin is  
de-asserted, the internal reset circuitry remains ac-  
tive for 5 MCLK cycles to insure resetting the syn-  
chronous circuitry in the device. The modulators  
are held in reset for 12 MCLK cycles after RESET  
is de-asserted. After a hardware or software reset,  
the internal registers (some of which may drive out-  
put pins) will be reset to their default values on the  
first MCLK received after detecting a reset event  
(see Table 3). The CS5460A will then assume its  
active state. (The term active state, as well as the  
other possible power states of the CS5460A, are  
described in Section 4.6).  
commands into the serial interface will result in ei-  
ther no operation or unexpected operation be-  
cause the CS5460A will not interpret the input  
command bits correctly. The CS5460A’s serial port  
must then be re-initialized. To initialize the serial  
port, any of the following actions can be performed:  
1) Power on the CS5460A. (Or if the device is al-  
ready powered on, recycle the power.)  
2) Hardware Reset.  
3) Issue the Serial Port Initialization Sequence,  
which is performed by clocking 3 (or more)  
SYNC1 command bytes (0xFF) followed by  
one SYNC0 command byte (0xFE) to the serial  
interface.  
4.6 CS5460A Power States  
Active state denotes the operation of CS5460A  
when the device is fully powered on (i.e., not in  
sleep state or stand-by state). Performing any of  
the following actions will insure that the CS5460A  
is operating in the active state:  
The reader should refer to Section 5 for a complete  
description of the registers listed in Table 3.  
Configuration Register:  
DC offset registers:  
Gain registers  
Pulse-Rate Register:  
Cycle-Counter Register:  
Timebase Register:  
Status Register:  
Mask Register:  
Control Register:  
AC offset registers:  
Power Offset Register:  
All data registers:  
0x000001  
0x000000  
0x400000  
0x0FA000  
0x000FA0  
0x800000  
(see Section 5)  
0x000000  
0x000000  
0x000000  
0x000000  
0x000000  
0x000000  
1) Power on the CS5460A. (Or if the device is al-  
ready powered on, recycle the power.)  
2) Hardware Reset  
3) Software Reset  
In addition to the three actions listed above, if the  
device is operating in sleep state or stand-by state,  
waking up the device out of sleep state or stand-by  
state (by issuing the Power-Up/Halt command) will  
also insure that the device is set into active state.  
But in order to send the Power-Up/Halt command  
to the device, the serial port has to be initialized.  
Therefore, successful wake-up of the device can  
be insured by writing the serial port initialization se-  
quence to the serial interface, prior to writing the  
Power-Up/Halt command.  
All unsigned data registers  
Table 3. Default Register Values upon Reset Event  
For a description of the sleep power state and the  
stand-by power state, see the Power Down Com-  
mand, located in Section 4.1.  
4.5 Serial Port Initialization  
It is possible for the serial interface to become un-  
synchronized with respect to the SCLK input. If  
this occurs, any attempt to clock valid CS5460A  
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