CS5012A, CS5014, CS5016
peaking in its output impedance characteristic at
signal frequencies or their harmonics.
pedance of less than 15 Ω at frequencies greater
than 10 kHz. Similarly, for the CS5014 with a
4.5V reference (275µV/LSB), better than
1/4 LSB accuracy can be insured with an output
impedance of 4Ω or less (maximum error of
40 µV). A 2.2 µF capacitor exhibits an imped-
ance of less than 4Ω at frequencies greater than
5kHz. For the CS5016 with a 4.5V reference
(69µV/LSB), better than 1/4 LSB accuracy can
be insured with an output impedance of less than
2Ω (maximum error of 20 µV). A 20 µF capaci-
tor exhibits an impedance of less than 2Ω at
frequencies greater than 16 kHz. A high-quality
tantalum capacitor in parallel with a smaller ce-
ramic capacitor is recommended.
A large capacitor connected between VREF and
AGND can provide sufficiently low output im-
pedance at the high end of the frequency
spectrum, while almost all precision references
exhibit extremely low output impedance at dc.
The magnitude of the current load on the external
reference circuitry will scale to the CLKIN fre-
quency. At full speed, the reference must supply a
maximum load current of 10 µA peak-to-peak
(1 µA typical). For the CS5012A an output im-
pedance of 15 Ω will therefore yield a maximum
error of 150 mV. With a 2.5V reference and LSB
size of 600 mV, this would insure better than 1/4
LSB accuracy. A 1 µF capacitor exhibits an im-
60
52
44
62
54
46
64
56
48
66
58
50
68
60
52
70
62
54
72
64
56
74
66
58
76
68
60
78 80/0
70 72/0
62 64/0
2
2
2
4
4
4
6
6
6
8
8
8
10
10
10
12
12
12
CS5016:
CS5014:
CS5012A:
CLKIN
EOC
LSB
Determined
MSB - 1
Determined
Determined
MSB
Determined
MSB - 2
Status
Coarse Charge
Fine Charge
EOT
t
d
HOLD
SCLK
SDATA
t
d
LSB+2
LSB+1
LSB
MSB
MSB - 1
Notes: 1. Synchronous (loopback) mode is illustrated. After EOC falls the converter goes into coarse charge mode for
6 CLKIN cycles, then to fine charge mode for 9 cycles, then EOT falls. In loopback mode, EOT trips HOLD
which captures the analog sample. Conversion begins on the next rising edge of CLKIN. If operated asynchro-
nously, EOT will remain low until after HOLD is taken low. When HOLD occurs the analog sample is captured
immediately, but conversion may not begin until four CLKIN cycles later. EOT will return high
when conversion begins.
2. Timing delay t (relative to CLKIN) can vary between 135 ns to 235 ns over the military temperature range
d
and over ± 10% supply variation
3. EOC returns high in 4 CLKIN cycles if A0 = 1 and CS = RD = 0 (Microprocessor Independent Mode);
within 4 CLKIN cycles after a data read (Microprocessor Mode); or 4 CLKIN cycles after HOLD = 0
is recognized on a rising edge of CLKIN/4.
Figure 9. Serial Output Timing
DS14F6
2-25
CIRRUS [ CIRRUS LOGIC ]
