CS5012A, CS5014, CS5016
The reset calibration always works perfectly, and
should be used instead of burst mode. The
CS5012’s and CS5012A/14/16’s very low drift
over temperature means that, under most circum-
stances, calibration will only need to be
performed at power-up, using reset.
temperature or to long-term aging, will generally
dominate total system error.
Microprocessor Interface
The CS5012A/14/16 feature an intelligent micro-
processor interface which offers detailed status
information and allows software control of the
self-calibration functions. Output data is available
in either 8-bit or 16-bit formats for easy interfac-
ing to industry-standard microprocessors.
The CS5012A/14/16 feature a background cali-
bration mode called "interleave." Interleave
appends a single calibration experiment to each
conversion cycle and thus requires no dead time
for calibration. The CS5012A/14/16 gathers data
between conversions and will adjust its transfer
function once it completes the entire sequence of
experiments (one calibration cycle per 2,014 con-
versions in the CS5012A and one calibration per
72,051 conversions in the CS5012, CS5014 and
CS5016). Initiated by bringing both the INTRLV
input and CS low (or hard-wiring INTRLV low),
interleave extends the CS5012A/14/16’s effective
conversion time by 20 CLKIN cycles. Other than
reduced throughput, interleave is totally transpar-
ent to the user. Interleave calibration should not
be used intermittently.
Strobing both CS and RD low enables the
CS5012A/14/16’s 3-state output buffers with
either output data or status information depending
on the status of A0. An address bit can be con-
nected to A0 as shown in Figure 4b thereby
memory mapping the status register and output
data. Conversion status can be polled in software
by reading the status register (CS and RD strobed
low with A0 low), and masking status bits S0-S5
and S7 (by logically AND’ing the status word
with 01000000) to determine the value of S6.
Similarly, the software routine can determine
calibration status using other status bits (see Ta-
ble 2). Care must be taken not to read the status
register (A0 low) while HOLD is low, or a soft-
ware reset will result (see Reset above).
The fact that the CS5012A/14/16 offer several
calibration modes is not to imply that the devices
need to be recalibrated often. The devices are
very stable in the presence of large temperature
changes. Tests have indicated that after using a
single reset calibration at 25 °C most devices ex-
hibit very little change in offset or gain when
exposed to temperatures from -55 to +125 °C.
The data indicated 30 ppm as the typical worst
case total change in offset or gain over this tem-
perature range. Differential linearity remained
virtually unchanged. System error sources outside
of the A/D converter, whether due to changes in
Alternatively, the End-of-Convert (EOC) output
can be used to generate an interrupt or drive a
DMA controller to dump the output directly into
memory after each conversion. The EOC pin falls
as each conversion cycle is completed and data is
valid at the output. It returns high within four
CLKIN cycles of the first subsequent data read
operation or after the start of a new conversion
cycle.
2-22
DS14F6
CIRRUS [ CIRRUS LOGIC ]
