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CS49326 参数 Datasheet PDF下载

CS49326图片预览
型号: CS49326
PDF下载: 下载PDF文件 查看货源
内容描述: 多标准音频解码器系列 [Multi-Standard Audio Decoder Family]
分类和应用: 解码器
文件页数/大小: 86 页 / 1343 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS49300 Family DSP  
is acceptable. This example can be easily expanded  
to fit other system requirements.  
11.3.1. Output Configuration Considerations  
1) All PCM output is 24-bit resolution  
For example if the host system has the following  
configuration:  
2) An SCLK frequency of at least 128Fs must be  
selected for the 20-bit multichannel (6 channel)  
mode.  
Address Checking: Disabled  
The above configuration is default so no  
configuration message is required.  
3) An SCLK frequency of at least 128Fs must be  
selected for the 24-bit multichannel (4 channel)  
mode.  
DAI: Left Justified  
PCM and Compressed data  
4) An SCLK frequency of at least 256Fs must be  
selected for the 24-bit multichannel (6 channel)  
mode.  
CDI: Not used  
The above configuration corresponds to  
INPUT A1 B1  
5) If the clocks to the audio ports are known to be  
corrupted, such as when a S/PDIF receiver goes  
out of lock, the DSP should undergo an  
application restart (if applicable), soft reset or  
hard reset. All three actions will result in the  
input FIFO being reset. Failure to do so may  
result in corrupted data being latched into the  
input FIFO and may result in corrupted data  
being heard on the outputs. This is not an issue  
when compressed data is being delivered, as it  
has sync words embedded in the stream which  
the DSP can lock to, but only when PCM data  
is being delivered. Certain application codes  
that are capable of processing PCM may now  
which corresponds to a configuration message of:  
0x800210  
0x3FBFC0  
0x800110  
0xC0002C  
0x800217  
0x8080FF  
0x80021A  
0x8080FF  
0x800117  
0x001000  
0x80011A  
0x001800  
have  
a
special feature called “PCM  
Robustness” which does alleviate the above  
problem, however you should still follow the  
above recommendation.  
DAO: Left Justified slave mode (LRCLK, SCLK  
inputs)  
MCLK @ 256Fs  
SCLK @ 64Fs  
11.4. Creating Hardware Configuration  
Messages  
The above configuration corresponds to  
OUTPUT A0 B1 C0 D0  
The single hardware configuration message that  
must be sent to the CS493XX after download or  
soft reset should be a concatenation of the  
messages in the previous sections. The complete  
hardware configuration message should be created  
by taking a message for each parameter (where the  
default is not acceptable) and concatenating the  
messages together. No messages need to be sent if  
the default configuration for a particular parameter  
which has a configuration message of:  
0x80027F  
0xFC7FFF  
0x80027C  
0xF01F00  
0x80027D  
0xF01F00  
78  
DS339PP4  
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