CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.23 T1GO (0x58) — Timer 1 Go Command
Write
load counter with high and low latch values and start to decrement (value
ignored)
Read
ignored
10.3.24 T1LAT (0x5C) — Timer 1 Latch Command
Write
Read
latch timer value in high and low count latches (value ignored)
ignored
10.3.25 IRQSTC (0x60) — IRQ C Interrupts Status
7
6
5
4
3
2
1
0
I
I
I
I
I
I
I I
The IRQC set of control registers control the effect of the IOP[7:0] I/O port bits on the main interrupts.
Their functionality is identical to that described for IRQB.
I
IOP[7:0] pins, active-low
Write
Read
ignored
status
0
1
inactive
active
10.3.26 IRQRQC (0x64) — IRQ C Interrupts Request
7
6
5
4
3
2
1
0
I
I
I
I
I
I
I I
I
IOP[7:0] pins, active-low
ignored
Write
Read
request, status bitwise AND’ed with mask
10.3.27 IRQMSKC (0x68) — IRQ C Interrupts Mask
7
6
5
4
3
2
1
0
I
I
I
I
I
I
I I
I
IOP[7:0] pins, active-low
set mask for each interrupt source
Write
0
1
do not form part of nIRQ
form part of nIRQ
Read
Reset
value set by write
set all ‘0’ (none affect nIRQ)
90
June 1997
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
