CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.63 VIDINITA (0x1DC) — Video DMA INIT A
31
30
29 28
4
3
0
L
E
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0 0 0 0
X
For normal CRT displays and single-panel LCD data, only the A registers are used. Load the INIT register
with the address within the frame buffer of the first qword to be displayed in the first raster at the top of
the screen. For dual-panel displays, load this register with the address of the first qword in the frame buffer
to be displayed at the top left of the upper panel.
Set the last bit (30) only if the INIT A register is programmed to the same value as the VIDEND register.
Using an INIT register allows hardware scrolling to be implemented by moving the position of the init reg-
ister within the frame buffer.
I
initial fetch location A
bits[31, 29] unused
bit[30] last bit
Write
0
1
not last fetch location
last fetch location
bits[28:4] video initial A DMA fetch location
bits[3:0] ignored
bit[31] ‘0’
Read
bit[30] last bit
0
1
not last fetch location
last fetch location
bit[29] ‘equal’ – output of comparator
bits[28:4] video initial A DMA fetch location
bits[3:0] always ‘0’
June 1997
105
ADVANCE DATA BOOK v2.0
MEMORY AND I/O PROGRAMMERS’ MODEL
CIRRUS [ CIRRUS LOGIC ]
