CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.64 VIDCR (0x1E0) — Video DMA Control
7
6
5
4
3
2
1
0
D 1 E 1 0 0 0 0
This register allows overall control for video DMA. Bit 7 selects between dual- and single-panel modes for
LCD driving; bit 5 enables video DMA.
NOTE: For driving normal CRT displays, set bit 7 to ‘0’.
D Dual-panel mode
E enable video/cursor DMA
Write
bit[7]
0
1
normal
Dual-panel mode
bit[6] ignored
bit[5]
0
1
disable
enable DMA
bits[4:0] ignored
Read
Reset
bits[7, 5] return above values
bit[6] always reads back ‘1’, DRAM mode
bits[4:0] reads as ‘10000’ (binary), indicates qword transfer
set to ‘0’ (disabled, Normal mode)
106
June 1997
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
