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CDB4365 参数 Datasheet PDF下载

CDB4365图片预览
型号: CDB4365
PDF下载: 下载PDF文件 查看货源
内容描述: 114分贝192千赫6声道D / A转换器 [114 dB, 192 kHz 6-Channel D/A Converter]
分类和应用: 转换器
文件页数/大小: 51 页 / 735 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4365  
3.7  
ATAPI Specification  
The CS4365 implements the channel mixing functions of the ATAPI CD-ROM specification. The  
ATAPI functions are applied per A-B pair. Refer to Table 9 on page 42 and Figure 19 for additional informa-  
tion.  
A Channel  
Volume  
Control  
Left Channel  
Audio Data  
MUTE  
AoutAx  
Σ
Σ
SDINx  
B Channel  
Volume  
Control  
Right Channel  
Audio Data  
MUTE  
AoutBx  
Figure 19. ATAPI Block Diagram (x = channel pair 1, 2, or 3)  
3.8  
Direct Stream Digital (DSD) Mode  
In software mode the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD mode. The DSD_DIF bits  
(Reg 04h) then control the expected DSD rate and MCLK ratio.  
The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD to analog conversion. The first  
method uses a decimation free DSD processing technique which allows for features such as matched PCM level  
output, DSD volume control, and 50kHz on chip filter. The second method sends the DSD data directly to the on-  
chip switched-capacitor filter for conversion (without the above mentioned features).  
The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style of data input. In  
this mode the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used for phase modulated 64x data (see  
Figure 20). Use of phase modulation mode may not directly effect the performance of the CS4365, but may lower  
the sensitivity to board level routing of the DSD data signals.  
The CS4365 can detect errors in the DSD data which does not comply with the SACD specification. The  
STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4365 to alter the incoming invalid DSD data.  
Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the MUTEC pins  
would be set according to the DAMUTE bit (Reg. 08h)).  
More information for any of these register bits can be found in the “Parameter Definitions” on page 45.  
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index)  
at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time however, performance at  
these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital volume control should be  
26  
DS670PP1  
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