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CAT28F010 参数 Datasheet PDF下载

CAT28F010图片预览
型号: CAT28F010
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位的CMOS闪存 [1 Megabit CMOS Flash Memory]
分类和应用: 闪存
文件页数/大小: 14 页 / 104 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT28F010  
SUPPLY CHARACTERISTICS  
Symbol  
Limits  
Parameter  
Min  
4.5  
0
Max.  
5.5  
Unit  
V
VCC  
VCC Supply Voltage  
VPPL  
VPPH  
VPP During Read Operations  
6.5  
V
VPP During Read/Erase/Program  
11.4  
12.6  
V
A.C. CHARACTERISTICS, Read Operation  
= +5V ±10%, unless otherwise specified.  
V
CC  
28F010-70(8) 28F010-90(7) 28F010-12(7)  
Min. Max. Min. Max. Min. Max.  
JEDEC Standard  
Symbol Symbol Parameter  
Unit  
ns  
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
CE Access Time  
Address Access Time  
OE Access Time  
70  
90  
120  
120  
120  
50  
AVAV  
ELQV  
AVQV  
GLQV  
AXQX  
RC  
CE  
70  
70  
28  
90  
90  
35  
ns  
ns  
ACC  
OE  
OH  
ns  
Output Hold from Address  
OE/CE Change  
0
0
0
ns  
(1)(6)  
OLZ  
t
t
t
t
t
t
t
t
t
OE to Output in Low-Z  
CE to Output in Low-Z  
OE High to Output High-Z  
CE High to Output High-Z  
0
0
0
0
0
0
ns  
ns  
ns  
ns  
µs  
GLQX  
(1)(6)  
ELZX  
LZ  
DF  
DF  
(1)(2)  
(1)(2)  
20  
30  
20  
30  
30  
40  
GHQZ  
EHQZ  
WHGL  
(1)  
-
Write Recovery Time  
Before Read  
6
6
6
(3)(4)(5)  
Figure 2. Highspeed A.C. Testing Input/Output  
Figure 1. A.C. Testing Input/Output Waveform  
Waveform(3)(4)(5)  
3.0 V  
2.4 V  
2.0 V  
0.8 V  
INPUT PULSE LEVELS  
REFERENCE POINTS  
INPUT PULSE LEVELS  
1.5 V  
REFERENCE POINTS  
0.45 V  
0.0 V  
5108 FHD F03  
5108 FHD F03A  
Testing Load Circuit (example)  
Testing Load Circuit (example)  
1.3V  
1.3V  
1N914  
1N914  
3.3K  
3.3K  
DEVICE  
UNDER  
TEST  
DEVICE  
UNDER  
TEST  
OUT  
OUT  
C
= 100 pF  
L
C
= 30 pF  
L
C
INCLUDES JIG CAPACITANCE  
5108 FHD F04  
L
C
INCLUDES JIG CAPACITANCE  
L
5108 FHD F05  
Note:  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.  
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.  
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.  
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.  
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.  
(7) For load and reference points, see Fig. 1  
(8) For load and reference points, see Fig. 2  
Doc. No. 25005-0A 2/98 F-1  
5