CAT28F010
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100K
10
Max.
Units
Cycles/Byte
Years
Test Method
(3)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
100
Volts
(3)(4)
ILTH
mA
CAPACITANCE T = 25°C, f = 1.0 MHz
A
Limits
Max.
6
Symbol
Test
Min
Units
pF
Conditions
VIN = 0V
(3)
CIN
Input Pin Capacitance
Output Pin Capacitance
VPP Supply Capacitance
(3)
COUT
10
25
pF
VOUT = 0V
VPP = 0V
(3)
CVPP
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 25005-0A 2/98 F-1
3
CATALYST [ CATALYST SEMICONDUCTOR ]
