CAT25C11/03/05/09/17
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max.
Units
pF
Conditions
VOUT=0V
VIN=0V
Output Capacitance (SO)
8
6
Input Capacitance (CS, SCK, SI, WP, HOLD)
pF
A.C. CHARACTERISTICS
SYMBOL PARAMETER
Limits
1.8V-6.0V
Min.
2.5V-6.0V
4.5V-5.5V
Test
Max. Min.
Max. Min. Max.
UNITS Conditions
tSU
tH
Data Setup Time
Data Hold Time
50
50
20
20
75
75
DC
20
20
40
40
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIH = 2.4V
CL = 100pF
VOL = 0.8V
VOH = 2.0v
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
5
50
2
DC
10
50
2
(1)
tRI
CL = 50pF
(note 2)
(1)
tFI
Input Fall Time
2
2
2
tHD
tCD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
40
40
40
40
CL = 100pF
(3)
tWC
tV
10
5
5
250
75
40
tHO
tDIS
tHZ
0
0
0
250
150
75
50
75
50
tCS
500
500
500
150
150
100
100
100
50
100
100
100
50
tCSS
tCSH
tWPS
tCSH
CS Setup Time
CS Hold Time
WP Setup Time
CS Hold Time
50
50
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V to 0.7V
CC
CC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C = 50pF
L
(3)
t
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
Doc. No. 1017, Rev. J
3
CATALYST [ CATALYST SEMICONDUCTOR ]
