CAT1320, CAT1321
Advance Information
EMBEDDED EEPROM OPERATION
SDA when SCL is HIGH. The CAT1320/21 monitors the
SDA and SCL lines and will not respond until this
condition is met.
The CAT1320 and CAT1321 feature a 32kbit
embedded serial EEPROM that supports the I2C Bus
data transmission protocol. This Inter-Integrated
Circuit Bus protocol defines any device that sends
data to the bus to be a transmitter and any device
receiving data to be a receiver. The transfer is
controlled by the Master device which generates the
serial clock and all START and STOP conditions for
bus access. Both the Master device and Slave device
can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition.TheMastersendstheaddressoftheparticular
slave device it is requesting. The four most significant
bitsofthe8-bitslaveaddressareprogrammableinmetal
and the default is 1010.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
The last bit of the slave address specifies whether a
ReadorWriteoperationistobeperformed.Whenthisbit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
thedatalinewhiletheclocklineishighwillbeinterpreted
as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT1320/21 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1320/21 then performs a Read or Write operation
depending on the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Doc. No. 25085, Rev. 00
8
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