CAT1320, CAT1321
Advance Information
Immediate/Current Address Read
Sequential Read
The CAT1320 and CAT1321 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For all devices,
N=E=4,095. The counter will wrap around to Zero and
continue to clock out valid data. After the CAT1320 and
CAT1321 receives its slave address information (with
the R/W bit set to one), it issues an acknowledge, then
transmits the 8-bit byte requested. The master device
does not send an acknowledge, but will generate a
STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1320 and CAT1321 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data.TheCAT1320andCAT1321willcontinuetooutput
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1320 and
CAT1321issentsequentiallywiththedatafromaddress
N followed by data from address N+1. The READ
operationaddresscounterincrementsalloftheCAT1320
and CAT1321 address bits so that the entire memory
array can be read during one operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishes to read. After the CAT1320 and CAT1321
acknowledges, the Master device sends the START
condition and the slave address again, this time with the
R/W bit set to one. The CAT1320 and CAT1321 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Figure 11. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
SLAVE
ADDRESS
A
DATA
15
8
7
SDA LINE
S
S
P
*
* *
*
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
*=Don’t Care Bit
Figure 12. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 25085, Rev. 00
12
CATALYST [ CATALYST SEMICONDUCTOR ]
