TMC3503
PRODUCT SPECIFICATION
Functional Description
SLEEP
The TMC3503 is a low-cost triple 8-bit CMOS D/A con-
verter designed to directly drive computer CRT displays at
pixel rates up to 80 Msps. It comprises three identical 8-bit
D/A converters with registered data inputs, common clock,
and internal voltage reference. An independent current
source allows sync to be added to any D/A converter output.
The SLEEP control, when HIGH, places the TMC3503 in a
power-down state. This function operates asynchronously.
D/A Outputs
Each D/A output is a current source. To obtain a voltage out-
put, a resistor must be connected to ground. Output voltage
depends upon this external resistor, the reference voltage,
and the value of the gain-setting resistor connected between
Digital Inputs
All digital inputs are TTL-compatible. Data are registered on
the rising edge of the CLK signal. The analog output
R
REF
and GND.
changes t
after the rising edge of CLK. There is one stage
DO
Normally, a source termination resistor of 75 Ohms is con-
nected between the D/A current output pin and GND near
the D/A converter. A 75 Ohm coaxial cable may then be con-
nected with another 75 Ohm termination resistor at the far
end of the cable. This "double termination" presents the D/A
converter with a net resistive load of 37.5 Ohms.
of pipeline delay on the chip. The guaranteed clock rates of
the TMC3503 are 80, 50, and 30 MHz.
SYNC and BLANK
SYNC and BLANK inputs control the output level
(Figure 1 and Table 1) of the D/A converters during CRT
retrace intervals. BLANK forces the D/A outputs to the
blanking level while SYNC turns off a separate current
The TMC3503 may also be operated with a single 75 Ohm
terminating resistor. To lower the output voltage swing to the
source which is brought off the chip through the IO pin.
S
desired range, the value of the resistor on R
increased.
should be
REF
Voltage Reference
data: 660 mV max.
pedestal: 54 mV
The TMC3503 has an internal bandgap voltage reference of
+1.235 Volts. An external voltage reference may be con-
nected to the V
pin, overriding the internal voltage refer-
REF
ence. All three D/A converters are driven from the same
reference.
sync: 286 mV
65-3503-02
A 0.1µF capacitor must be connected between the COMP
Figure 1. Nominal Output Levels
pin and V
to stabilize internal bias circuitry and ensure
DD
low-noise operation.
IO may be connected to any one D/A output, or used inde-
S
pendently. It is commonly tied to the green D/A converter for
“Sync on Green” operation. This connection adds a 40 IRE
sync pulse to the D/A output and brings that D/A output to
0.0 Volts during the sync tip. SYNC and BLANK are regis-
tered on the rising edge of CLK.
Power and Ground
The TMC3503 D/A converter requires a single +5.0 Volt
power supply. The analog (V ) power supply voltage
should be decoupled to GND to reduce power supply
induced noise. 0.1µF decoupling capacitors should be placed
as close as possible to the power pins.
DD
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = LOW, data
inputs and the pedestal are disabled.
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic distor-
tion or reduced signal-to-noise performance. All ground pins
should be connected to a common solid ground plane for
best performance.
WHITE
The WHITE control drives all three D/As to full-scale, over-
riding the data inputs. It is overridden by the BLANK input,
and is independent of SYNC.
2
REV. 1.02 11/24/99
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
