Figure 5 – Timing Diagram 2
CLK
t
D1
Table II – Timing Parameters
Parameter
CLK high to Data Valid
OE inactive to HiZ
OE active to Data Valid
1
Symbol
t
D1
t
D2
t
D3
Min Typ Max
18
10
10
24
16
16
40
1
30
30
Units
ns
ns
ns
Digital
Outputs
t
D2
t
D3
Conditions: load capacitance = 20 pF, V
OH
= 3.3 V
OE
FFT Plot
Typical Differential Linearity Error (DLE)
Test Conditions:
ƒ
IN
= 2 MHz
ƒ
CLK
= 4.4 MHz
PGA Gain = 18 dB
R
EXT
= 1.08 kΩ
ADC Input (Post PGA) = –5.4 dBFS
T
A
= +25 °C
Test Conditions:
ƒ
IN
= 75 kHz
ƒ
CLK
= 4.4 MHz
DLE (LSB)
PGA Gain = 0 dB
Near Full-Scale Input
Two-Tone Intermodulation FFT
100
95
90
85
80
Spurious-Free Dynamic Range
0.9 MHz, low
0.9 MHz, med
0.9 MHz, high
2 MHz, high
2 MHz, med
SFDR (dBc)
75
70
2 MHz, low
65
60
55
50
3 MHz, high
3 MHz, med
Test Conditions:
ƒ
1
= 890 kHz
ƒ
2
= 900 kHz
ƒ
CLK
= 4.4 MHz
PGA Gain = 6 dB
3 MHz, low
R
EXT
= 1.43 kΩ
ADC Input (Post PGA) = –8.0 dBFS
T
A
= +25 °C
45
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
Composite Level at ADC Input (dBFS)
0
5 V
P-P
Test Conditions:
Med: R
EXT
=1.24 kΩ @109 mA
10 MSPS, 5 V, 25 °C
Low: R
EXT
=1.43 kΩ @96 mA High: R
EXT
=1 kΩ @129 mA
SPT8100
8
1/9/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
