Figure 3 – Timing Diagram 1
n+1
n
n+2
n+3
n+4
n+5
n+8
Analog In
n+6
n+7
CLK
t
D
D0D15
OVR
n
n+1
n+2
INPUT/OUTPUT TIMING
The SPT8100 implements a simple interface: the 16 ADC
outputs appear on the pins D15–D0 as a parallel word syn-
chronous with the ADC sampling clock. D0 is the LSB and
D15 is the MSB. The timing diagram for the ADC digital
outputs is shown in figure 3. The data is sampled at the fall-
ing edge of the clock. The ADC sampling clock is at the
same frequency as CLK.
The output data is updated on the rising edge of CLK with
a clock latency of 5.5 clock cycles.
OUTPUT ENABLE
The ADC digital outputs are enabled by the active high
output enable pin (OE).
OE = 1: ADC digital outputs are enabled
OE = 0: ADC digital outputs are high-impedance
(tri-stated)
DIGITAL CODE RANGE AND
OUT-OF-RANGE DETECTION
The output format of the ADC digital data is offset binary.
Due to the calibration algorithm used, there is a slight loss
in digital code range from the ADC. Instead of FFFFH and
0000H at the extremes of the range, the actual maximum
and minimum codes are less than that by 1.6% at both
ends of the scale, and vary from chip to chip. Effectively,
this is a loss in dynamic range of a few tenths of a dB, and
is negligible in many applications. The out-of-range func-
tion is defined accordingly, and sets the state of the active
high digital output OVR, as follows:
OVR is HIGH if the ADC digital code is greater
than or equal to FC00H or less than or equal to
03FFH.
(See figure 4.)
If the output code exceeds FC00(max) or 03FF(min), this
implies that output is clipping. Therefore, once these limits
are crossed, the second harmonic becomes significant
and degrades performance.
Figure 4 – ADC Digital Code Range and Overrange
Bit Function
FFFFH
OVR = 1
FC00H
ADC
Digital Code
Range
03FFH
OVR = 1
0000H
0
64512
65535
1.6% FSR
OUTPUT LOGIC LEVEL
The voltage levels on the D15–D0 lines and OVR are
CMOS levels: the HIGH level is determined by the power
supply voltage on the OV
DD
pin, which can be set indepen-
dently of the other supply pins on the device over the range
from 3.0 V to 5.25 V (3.3 V typical). The RDY pin level is
determined by DV
DD
(+5 V).The external digital output
buffers should be placed as close as possible to the
SPT8100 digital outputs to minimize any line reflections
that would cause performance degradation.
ADC REFERENCES
The ADC full-scale range is set by reference voltages gen-
erated on chip. These two reference voltages appear on
pins V
RT
and V
RB
; nominally their difference is 2.5 V. The
references are not designed to be overdriven. The V
RT
and
V
RB
pins should be very carefully decoupled on the board
using as short a trace as possible. Some optimization of
the decoupling may be required, as shown in the typical
interface circuit diagram. The smallest capacitor should be
the closest one to the chip. (Refer to the typical interface
circuit diagram.)
OVR = Ø
1023
1.6% FSR
SPT8100
7
1/9/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
