DEVICE OVERVIEW
The SPT8100 combines a high-resolution 5 MSPS 16-bit
ADC, a built-in reference, and a programmable gain amp-
lifier (PGA) with resistive input impedance in a 44-pin
package.
The device includes a digitally calibrated pipeline ADC,
which is calibrated on assertion of a simple reset signal.
The combination of low noise, high linearity, a high-input
impedance buffer (with programmable gain), wideband
S/H, on-board voltage references, and simple digital inter-
face (16-bit parallel output word synchronous with the
master sampling clock) makes the SPT8100 extremely
easy to use in a wide variety of systems.
For optimum performance, the analog inputs should be
driven differentially, and may be AC-coupled or DC-
coupled to a source. Typical applications include high-per-
formance data acquisition systems, automatic test equip-
ment, and wideband digital communications receivers
such as wireless basestations.
ADC CLOCK
The chip requires a single low-jitter clock to be applied at
the CLK pin, with nominal 40–60% duty cycle. All clock
generation is performed internally and all converter and
S/H clocks in the ADC path are directly derived from CLK.
If the sample rate is changed by more than a factor of 2,
the device must be recalibrated using the
RS
(reset) pin.
DEVICE STARTUP/INITIALIZATION SEQUENCE
Note: This initialization sequence is
required.
Without
it, the device will not work.
Allow sufficient time for the analog blocks on the SPT8100
to power on and come up to their quiescent DC states.
Allowance may also be needed for thermal time constants
associated with the package/board.
On powerup, the SPT8100’s
RS
(reset) should be held low
for at least three clock cycles. The power supply voltages
applied to the device must be stable during this time. The
clock signal (CLK) must be running for at least three clock
cycles prior to the rising edge of
RS
, and must continue
running.
When the
RS
signal goes from low to high, calibration is ini-
tiated. RDY is driven low two clock cycles after the rising
edge of
RS
, and will stay low for 150 ms with a 5 MHz clock.
When the initialization is complete, RDY returns high and
the device is ready for normal operation. Note that the cali-
bration of the ADC can be interrupted (before completion)
by changing the
RS
signal from high to low, which will
cause another reset to occur. When
RS
goes from low back
to high, another calibration cycle will begin.
RDY cannot be tri-stated: it is always driven either high or
low. The CLK must be constantly running throughout the
OPERATIONAL DESCRIPTION
The following sections describe in greater detail individual
blocks and functions of the SPT8100.
The incoming analog differential signal (maximum level 5 V
peak-to-peak differential) enters the device at the pins
V
IN
+/V
IN
–. The analog signal path is partitioned into a pro-
grammable gain amplifier (PGA) and an ADC. The PGA
has maximum gain of +19.5 dB; the gain is set by the digi-
tal control signals GS0 to GS2.
The output of the PGA is fed directly to the ADC, which
samples at a rate equal to the CLK frequency and outputs
a 16-bit wide parallel word. The ADC uses a pipeline multi-
stage architecture. Latency is 5.5 clock cycles.
Figure 1 – Device Initialization Timing
PWR ON
N+7
N+8
A
IN
N+4
N+6
N+5
CLK
RS
3 clock cycles min
2 clock cycles
5 ns typ
Initialization period: 150 ms with 5 MHz clock
RDY
24 ns typ
D
OUT
Requires external reset on powerup
INVALID DATA
N
N+1
N+2
SPT8100
4
1/9/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
