Figure 2a – Typical Interface Circuit
1.0
+
Gain Control
Reset
Output
Enable Clock
(active Hi) Input
.01
1.43K
R
EXT
Transformer
BIAS
C
RS GS2 GS1 GS0
BIAS
R
V
CM
V
IN
+
R
T
(50)
V
IN
–
Mini-Circuit
T1-6T
OE
CLK
RDY
16
A
IN
SPT8100
V
RT
V
RB
0.1
1nF
AV
DD
DV
DD
AGND DGND OGND
D0–15
Logic
Interfacing
Circuit
0.1
+
4.7
+
10
OVR
OV
DD
0.1
10
10
0.1
+
+A5V
+
FB1
+A3.3/5V
+D3.3/5V
Figure 2b – Typical Interface Circuit
1.0
+
Gain Control
Reset
Output
Enable Clock
(active Hi) Input
.01
1.43K
R
EXT
Transformer
BIAS
C
RS GS2 GS1 GS0
BIAS
R
V
CM
V
IN
+
R
T
(50)
V
IN
–
Mini-Circuit
T1-6T
OE
CLK
RDY
16
A
IN
SPT8100
V
RT
V
RB
0.1
1nF
AV
DD
DV
DD
AGND DGND
OGND
0.1
0.1
10
FB1
D0–15
Logic
Interfacing
Circuit
0.1
+
4.7
+
10
OVR
OV
DD
+
ƒ
S
(MSPS) R
EXT
(kΩ)
Ω
–5
–2
–5
–2
1.43
2.00
1.24
1.00
FB2
FB3
ƒ
IN
<2 MHz
<2 MHz
•2 MHz
•2 MHz
10
+
+A5V
+D3.3/5V
800
Ω
– R
EXT
– 2.5 kΩ
Notes:
1. To avoid device latch-up, closely follow either figure 2a or 2b, depending on what is available in the system. The difference between figure 2a
and 2b is in the grounding.
2. FB = ferrite bead. FB1 must be placed as close to the device as possible.
3. R
EXT
= 1.43 kΩ, optimized for ƒ
S
= 5 MSPS. Refer to the above table for recommended value of R
EXT
with respect to ƒ
S
and ƒ
IN
.
4. R
T
is A
IN
source termination resistor.
5. Power supplies and references pins must have adequate decoupling. Surface-mount capacitors are highly recommended. The smallest value
of capacitors are to be placed as close to the pin as possible.
SPT8100
6
1/9/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
