ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Supply Voltages
AV
DD
...................................................................... +6 V
DV
DD
..................................................................... +6 V
OV
DD
..................................................................... +6 V
Input Voltages
Analog Input ................................. –0.5 V to V
DD
+0.5 V
CLK Input ............................................................... V
DD
AV
DD
– DV
DD
.................................................. ±100 mV
Delta between AGND, DGND, and OGND ...... ±100 mV
Output
Digital Outputs .................................................... 10 mA
Temperature
Operating Temperature ........................... –40 to +85 °C
Junction Temperature ...................................... +175 °C
Lead Temperature (soldering 10 seconds) ...... +300 °C
Storage Temperature ............................ –65 to +150 °C
Note 1: Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions in
typical applications.
ELECTRICAL SPECIFICATIONS
T
A
=T
MIN
to T
MAX
, AV
DD
=DV
DD
=+5.0 V, OV
DD
= 3.3 V, ƒ
S
=5 MSPS, 2.5 V
PP
input span, Gain=0 dB, R
EXT
=1.43 kΩ, unless
otherwise specified.
PARAMETERS
Resolution
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
Gain Error
1
Offset Error
2
Analog Input (into PGA)
Differential Input Voltage Range
V
IN
+, V
IN
–
Input Capacitance
PGA Gain = 0 dB
Input Resistance
3
Input Bandwidth
4
PGA Gain = 0 dB
Input Common Mode Voltage Range
Programmable Gain Amp
Composite Input-Referred
Noise Floor
ƒ
IN
> 300 kHz
PGA Gain = 0 dB
PGA Gain = 2.9 dB
PGA Gain = 5.8 dB
PGA Gain = 11.8 dB
PGA Gain = 14.8 dB
PGA Gain = 17.5 dB
PGA Gain = 19.5 dB
V
V
IV
IV
TEST
CONDITIONS
TEST
LEVEL
MIN
15.9
SPT8100
TYP
16
±1.25
±0.5
–7.5
–5
+7.5
+5
MAX
UNITS
Bits
LSB
LSB
%FSR
%FSR
V
IV
IV
V
V
5
15
1.15
5.5
12
2.40
3.65
V
PPD
pF
kΩ
MHz
V
PGA Range
PGA Gain Steps
3
PGA Gain Accuracy
Conversion Characteristics
Maximum Conversion Rate
Pipeline Delay (Latency)
5
Reset Pulse Time (
RS
)
Reset Calibration Time
References and External Bias
V
RT
– V
RB
(Internal Ref)
Bias Resistor Range (External)
V
CM
Output Voltage
V
CM
Output Current
V
RT
V
RB
Total gain error of PGA and ADC using internal references.
2
Total offset error of PGA and ADC relative to mid-scale.
3
See table I for input resistance as a function of PGA gain.
1
4
5
V
V
V
V
V
V
V
V
VI
VI
VI
IV
IV
V
VI
V
IV
IV
V
V
1.4
1.5
1.6
2.0
2.3
2.6
2.8
19.5
0,2.9,5.8,11.8,14.8,17.5,19.5
±0.3
5
5.5
3
150
2.375
800
2.275
3.45
0.95
2.5
1430
2.40
3.65
1.15
2.625
2500
2.525
47
3.85
1.35
LSB
RMS
LSB
RMS
LSB
RMS
LSB
RMS
LSB
RMS
LSB
RMS
LSB
RMS
dB
dB
dB
MSPS
Clocks
Clocks
ms
V
Ω
V
µA
V
V
FS = 5 MSPS
Input bandwidth is a frequency to which the fundamental energy drops by 3 dB
The input is sampled on the falling edge of the clock and is available on the
output after the rising edge of the clock, 5.5 clock cycles later.
SPT8100
2
1/9/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
