Data Sheet
Electrical Characteristics - CDK2308A
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
61.7
61.6
61.6
61.6
61.7
61.6
60.5
61.6
80
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
60
SNR
Signal to Noise Ratio
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
60
70
SNDR
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
81
dBc
70
dBc
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
80
dBc
-90
-90
-90
-90
-80
-81
-70
-80
10
dBc
-80
-70
9.7
dBc
dBc
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
dBc
dBc
HD3
dBc
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
bits
9.9
9.8
9.9
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
bits
FIN = 20MHz
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-105
dBc
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
8.2
1.7
2.8
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
2.3
mA
Analog Power Dissipation
Digital Power Dissipation
14.8
8.8
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
23.6
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.9
15.2
7.7
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
20
MSPS
MSPS
15
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www.cadeka.com
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