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CDK2308BILP64 参数 Datasheet PDF下载

CDK2308BILP64图片预览
型号: CDK2308BILP64
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道, 20/40/ 65 / 80MSPS , 10位模拟 - 数字转换器 [Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters]
分类和应用: 转换器
文件页数/大小: 15 页 / 958 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Data Sheet  
Electrical Characteristics  
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50MSPS clock, 50% clock duty cycle,  
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
DC Accuracy  
No Missing Codes  
Offset Error  
Guaranteed  
1
Midscale offset  
LSB  
%FS  
%FS  
LSB  
LSB  
V
Gain Error  
Full scale range deviation from typical  
Gain matching between channels  
12-bit level  
-6  
6
Gain Matching  
±0.05  
±0.15  
±0.2  
DNL  
Differential Non-Linearity  
Integral Non-Linearity  
Common Mode Voltage Output  
ILE  
12-bit level  
VCMO  
VAVDD/2  
Analog Input  
VCMI  
Input Common Mode  
Analog input common mode voltage  
Differential input voltage range  
Differential input capacitance  
Input bandwidth, full power  
VCM -0.1  
500  
VCM +0.2  
V
2
2
Vpp  
pF  
VFSR  
Full Scale Range  
Input Capacitance  
Bandwidth  
MHz  
Power Supply  
AVDD, DVDD  
Supply voltage to all 1.8V domain pins.  
See Pin Configuration and Description  
1.7  
1.7  
1.8  
2.5  
2
V
V
Core Supply Voltage  
I/O Supply Voltage  
Output driver supply voltage (OVDD).  
Must be higher than or equal to Core Supply  
3.6  
OVDD  
Voltage (VOVDD ≥ VOCVDD  
)
©2009 CADEKA Microcircuits LLC  
www.cadeka.com  
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