Data Sheet
Electrical Characteristics - CDK2308D
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
60
61.6
61.2
61.3
61.3
61.3
60.7
61
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
60
70
SNDR
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
59
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
75
75
dBc
75
dBc
65
dBc
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
-80
-70
9.7
-90
-95
-90
-80
-75
-75
-75
-65
9.9
9.8
9.8
9.5
dBc
dBc
dBc
dBc
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
dBc
dBc
HD3
dBc
dBc
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
bits
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
bits
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-95
dBc
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
26.5
6.1
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
9.5
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
7.6
mA
Analog Power Dissipation
Digital Power Dissipation
47.7
30
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
77.7
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.1
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
46.1
18.3
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
80
MSPS
MSPS
65
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www.cadeka.com
9
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