Data Sheet
Electrical Characteristics - CDK1307D
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Performance
Parameter
Conditions
F
IN
= 8MHz
Min
70.4
Typ
72
71.7
71.2
70.7
Max
Units
CDK1307
Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
bits
bits
bits
mA
mA
mA
mA
mW
mW
mW
μW
mW
MSPS
65
MSPS
SNR
Signal to Noise Ratio
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
69.5
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
74
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
-80
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
-74
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
F
IN
= 8MHz
11.3
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
≃
FS/2
70.5
70.5
70.5
70.3
77
78
78
78
-95
-90
-90
-85
-77
-78
-78
-78
11.4
11.4
11.4
11.4
24.5
SINAD
Signal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2
Second order Harmonic Distortion
HD3
Third order Harmonic Distortion
ENOB
Effective number of Bits
Power Supply
AI
DD
DI
DD
Analog Supply Current
Digital Supply Current
Digital core supply
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT enabled
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
Power Dissipation, Sleep mode
80
2.9
6.1
4.1
44.1
15.5
59.6
9.1
24.1
OI
DD
Output Driver Supply
Analog Power Dissipation
Digital Power Dissipation
Total Power Dissipation
Power Down Dissipation
Sleep Mode
Rev 1A
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
©2009 CADEKA Microcircuits LLC
www.cadeka.com
9
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
