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CDK1307_09 参数 Datasheet PDF下载

CDK1307_09图片预览
型号: CDK1307_09
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 10/20 /40 /八十○分之六十五/ 100MSPS , 12月13日位模拟至数字转换器(ADC ) [Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit Analog-to-Digital Converters (ADCs)]
分类和应用: 转换器
文件页数/大小: 15 页 / 1240 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Data Sheet  
Electrical Characteristics  
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,  
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
DC Accuracy  
No Missing Codes  
Guaranteed  
1
Offset Error  
Midscale offset  
mV  
%FS  
LSB  
LSB  
V
Gain Error  
Full scale range deviation from typical  
12-bit level  
-6  
6
DNL  
Differential Non-Linearity  
Integral Non-Linearity  
Common Mode Voltage Output  
±0.2  
±0.6  
INL  
12-bit level  
VCMO  
VAVDD/2  
Analog Input  
VCMI  
Input Common Mode  
Analog input common mode voltage  
Differential input voltage range,  
VCM -0.1  
VCM +0.2  
V
2.0  
1.0  
Vpp  
Vpp  
Full Scale Range, Normal  
VFSR  
Differential input voltage range, 1V  
(see section Reference Voltages)  
Full Scale Range, Option  
Input Capacitance  
Bandwidth  
Differential input capacitance  
Input bandwidth, full power  
2
pF  
500  
MHz  
Power Supply  
Supply voltage to all 1.8V domain pins.  
See Pin Configuration and Description  
1.7  
1.7  
1.8  
2.5  
2.0  
3.6  
V
V
AVDD,  
DVDD  
Core Supply Voltage  
I/O Supply Voltage  
Output driver supply voltage (OVDD).  
Must be higher than or equal to Core Supply  
OVDD  
Voltage (VOVDD ≥ VOCVDD  
)
©2009 CADEKA Microcircuits LLC  
www.cadeka.com  
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