Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1 dBFS input signal, 5pF capacitive load, unless otherwise noted)
Symbol
Clock Inputs
Parameter
Duty Cycle
Compliance
Input Range
Input Common Mode Voltage
Input Capacitance
Conditions
Min
20
Typ
Max
80
Units
CDK1307
Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs
% high
mV
pp
V
pp
CMOS, LVDS, LVPECL, Sine Wave
Differential input swing
Differential input swing, sine wave clock input
Keep voltages within ground and voltage of OV
DD
Differential
400
1.6
0.3
2
V
OVDD
-0.3
V
pF
Timing
T
PD
T
SLP
T
OVR
T
AP
Start Up Time from Power Down
Start Up Time from Sleep
Out Of Range Recovery Time
Aperture Delay
Aperture Jitter
Pipeline Delay
Output Delay
Output Delay Relative to CLK_EXT
5pF load on output bits (see timing diagram)
See timing diagram
V
OVDD
≥ 3.0V
V
OVDD
= 1.7V – 3.0V
V
OVDD
≥ 3.0V
V
OVDD
= 1.7V – 3.0V
3
1
2
0.8
•
V
OVDD
0
0
-10
-10
3
-0.1
+
V
OVDD
0.1
Post-driver supply voltage equal to pre-driver
supply voltage V
OVDD
= V
VDVDD
Post-driver supply voltage above 2.25V
(1)
10
5
0.8
0.2
•
V
OVDD
10
10
From Power Down Mode to Active Mode
From Sleep Mode to Active Mode
1
0.8
<0.5
12
10
6
900
20
clk cycles
clk cycles
clk cycles
ns
ps
clk cycles
ns
ns
V
V
V
V
μA
μA
pF
V
V
pF
pF
ε
RMS
T
LAT
T
D
T
DC
Logic Inputs
V
IH
V
IL
I
IH
I
IL
C
I
High Level Input Voltage
Low Level Input Voltage
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Max Capacitive Load
Logic Outputs
V
OH
V
OL
C
L
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
10
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
