SYNCHRONIZATION WITH THE DIGITAL
AUDIO SYSTEM
synchronization occurs followed by tADCDLY2 delay time. If
LRCIN is synchronized with 5 or less bit clocks to the system
clock, operation will be normal. Figure 9 illustrates the effects
on the output when synchronization is lost. Before the outputs
are forced to bipolar zero (<1/fS seconds), the outputs are not
defined and some noise may occur. During the transitions
between normal data and undefined states, the output has
discontinuities, which will cause output noise.
The PCM3002/3003 operates with LRCIN synchronized to
the system clock. PCM3002/3003 does not require any spe-
cific phase relationship between LRCIN and the system
clock, but there must be synchronization. If the synchroniza-
tion between the system clock and LRCIN changes more than
6 bit clocks (BCKIN) during one sample (LRCIN) period
because of phase jitter on LRCIN, internal operation of the
DAC will stop within 1/fS, and the analog output will be
forced to bipolar zero (0.5VCC) until the system clock is re-
synchronized to LRCIN followed by tDACDLY2 delay time.
Internal operation of the ADC will also stop within 1/fS, and
the digital output codes will be set to bipolar zero until re-
ZERO FLAG OUTPUT: PCM3002 ONLY
Pin 16 is an open-drain output, used as the infinite zero
detection flag on the PCM3002 only. When input data is
continuously zero for 65,536 BCKIN cycles, ZFLG is LOW,
otherwise, ZFLG is in a high-impedance state.
Reset Removal or Power Down OFF
Internal Reset
or Power Down
Ready/Operation
Reset
Power Down
tDACDLY1 (16384/fS)
VCOM
GND
Zero
DAC VOUT
(0.5VCC
)
tADCDLY1 (18436/fS)
Zero
Normal Data(1)
ADC DOUT
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
FIGURE 8. DAC Output and ADC Output for Reset and Power Down.
Synchronization
Lost
Resynchronization
State of
Synchronization
Synchronous
Asynchronous
Synchronous
within
1/fS
tDACDLY2 (32/fS)
Undefined Data
Undefined Data
VCOM
(= 1/2 x VCC
Normal
Normal
DAC VOUT
Normal
)
tADCDLY2 (32/fS)
ADC DOUT
Normal(1 )
Zero
NOTES: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
FIGURE 9. DAC Output and ADC Output for Loss of Synchronization.
®
PCM3002/3003
16
BB [ BURR-BROWN CORPORATION ]
