PROGRAM REGISTER 2
A (1:0): Bit 10, 9 Register Address
These bits define the address for REGISTER 2:
IZD:
Bit 4
DAC Infinite Zero Detection Circuit
Control
This bit enables the Infinite Zero Detection Circuit
in PCM3002. When enabled, this circuit will dis-
connect the analog output amplifier from the delta-
sigma DAC when the input is continuously zero for
65,536 consecutive cycles of BCKIN.
A1
A0
1
0
Register 2
res:
Bit 15:11, 6 Reserved
These bits are reserved and should be set to “0”.
PDAD: Bit 8 ADC Power-Down Control
IZD
0
1
Infinite Zero Detection Disabled (default)
Infinite Zero Detection Enabled
This bit places the ADC section in the lowest
power consumption mode. The ADC operation is
stopped by cutting the supply current to the ADC
section, and DOUT is fixed to zero during ADC
Power-down mode enable. Figure 8 illustrates the
ADC DOUT response for ADC power-down ON/
OFF. This does not affect the DAC operation.
OUT:
Bit 3
DAC Output Enable Control
When set to “1”, the outputs are forced to VCC/2
(bipolar zero). In this case, all registers in
PCM3002 hold the present data. Therefore, when
set to “0”, the outputs return to the previous
programmed state.
OUT
PDAD
DAC POWER-DOWN
0
1
Power Down Mode Disabled (default)
Power Down Mode Enabled
0
1
DAC Outputs Enabled (default normal operation)
DAC Outputs Disabled (forced to BPZ)
BYPS: Bit 7
ADC High-Pass Filter Bypass Control
DEM (1:0):Bit 2,1
DAC De-emphasis Control
These bits select the de-emphasis mode as shown
below:
This bit enables or disables the high-pass filter for
the ADC.
DEM1
DEM0
BYPS
0
0
1
0
1
0
De-emphasis 44.1kHz ON
De-emphasis OFF (default)
De-emphasis 48kHz ON
0
1
High-Pass Filter Enabled (default)
High-Pass Filter Disabled (bypassed)
1
1
De-emphasis 32kHz ON
PDDA: Bit 6
DAC Power-Down Control
This bit places the DAC section in the lowest power
consumption mode. The DAC operation is stopped
by cutting the supply current to the DAC section
and VOUT is fixed to GND during DAC Power-
Down Mode enable. Figure 8 illustrates the DAC
VOUT response for DAC Power-Down ON/OFF.
This does not affect the ADC operation.
MUT:
Bit 0
DAC Soft Mute Control
When set to “1”, both left and right-channel DAC
outputs are muted at the same time. This muting
is done by attenuating the data in the digital filter,
so there is no audible click noise when soft mute
is turned on.
MUT
PDDA
0
1
Mute Disable (default)
Mute Enable
0
1
Power-Down Mode Disabled (default)
Power-Down Mode Enabled
ATC:
Bit 5
DAC Attenuation Channel Control
PROGRAM REGISTER 3
A (1:0): Bit 10:9 Register Address
These bits define the address for REGISTER 3:
When set to “1”, the REGISTER 0 attenuation
data can be used for both DAC channels. In this
case, the REGISTER 1 attenuation data is ig-
nored.
A1
A0
1
1
Register 3
ATC
0
1
Individual Channel Attenuation Data Control (default)
Common Channel Attenuation Data Control
res:
Bit 15:11, 8:6, 4:0
Reserved
These bits are reserved, and should be set to “0”.
®
19
PCM3002/3003
BB [ BURR-BROWN CORPORATION ]
