POWER-ON RESET
SYSTEM CLOCK
Both the PCM3002 and PCM3003 have internal power-on
reset circuitry. Power-on reset occurs when system clock
(SYSCLK) is active and VDD > 2.2V. For the PCM3003, the
SYSCLK must complete a minimum of 3 complete cycles
prior to VDD > 2.2V to ensure proper reset operation. The
initialization sequence requires 1024 SYSCLK cycles for
completion, as shown in Figure 6. Figure 8 shows the state
of the DAC and ADC outputs during and after the reset
sequence.
The system clock for PCM3002/3003 must be either 256fS,
384fS or 512fS, where fS is the audio sampling frequency. The
system clock should be provided at the SYSCLK input (pin 9).
The PCM3002/3003 also has a system clock detection circuit
which automatically senses if the system clock is operating at
256fS, 384fS, or 512fS. When 384fS or 512fS system clock is
used, the clock is divided into 256fS automatically. The 256fS
clock is used to operate the digital filters and the delta-sigma
modulators.
EXTERNAL RESET
Table I lists the relationship of typical sampling frequencies
and system clock frequencies, while Figure 5 illustrates the
system clock timing.
The PCM3002 includes a reset input, RST (pin 7), while the
PCM3003 utilizes both PDAD (pin 7) and PDDA (pin 8) for
external reset control. As shown in Figure 7, the external
reset signal must drive RST or PDAD/PDDA low for a
minimum of 40 nanoseconds while SYSCLK is active in
order to initiate the reset sequence. Initialization starts on the
rising edge of RST or PDAD/PDDA, and requires 1024
SYSCLK cycles for completion. Figure 8 shows the state of
the DAC and ADC outputs during and after the reset se-
quence.
SAMPLING RATE FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY
(MHz)
256fS
384fS
512fS
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9340
18.4320
16.3840
22.5792
24.5760
TABLE I. System Clock Frequencies.
tSCKH
"H"
"L"
0.7V
SYSCLK
0.3VDD
tSCKL
1/256fS,1/384fS,or 1/512fS
System Clock Pulse Width High tSCKH
System Clock Pulse Width Low tSCKL
12ns
12ns
(min)
(min)
FIGURE 5. System Clock Timing.
2.4V
2.2V
2.0V
VDD
Reset
Reset Removal
Internal Reset
SYSCLK
1024 System Clock Periods
FIGURE 6. Internal Power-On Reset Timing.
tRST = 40ns minimum
RST
or
PDAD and PDDA
tRST
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
SYSCLK
FIGURE 7. External Forced Reset Timing.
®
15
PCM3002/3003
BB [ BURR-BROWN CORPORATION ]
