LOP:
Bit 5
ADC to DAC Loop-Back Control
LRP:
Bit 1
Polarity of LRCIN Applies only to
Formats 0 through 2.
When this bit is set to “1”, the ADC’s audio data
is sent directly to the DAC. The data format will
default to I2S. In Format 3 (I2S Frame), Loop-
back is not supported.
LRP
0
1
Left-channel is “H”, Right-channel is “L”. (default)
Left-channel is “L”, Right-channel is “H”.
LOP
0
1
Loop-back Disable (default)
Loop-back Enable
FMT (1,0) Bit 3:2
Audio Data Format Select
These bits determine the input and output audio
data formats.
FMT1 FMT0
DAC
ADC
Data Format
Data Format
NAME
0
0
1
1
0
1
0
1
16-bit, MSB-first,
Right-justified
16-bit, MSB-first,
Left-justified
Format 0 (default)
20-bit, MSB-first,
Right-justified
20-bit, MSB-first,
Left-justified
Format 1
Format 2
Format 3
20-bit, MSB-first,
Left-justified
20-bit, MSB-first,
Left-justified
20-bit, MSB-first,
I2S
20-bit, MSB-first,
I2S
+3V Analog VCC
PCM3002/3003
0.1µF
0.1µF and 10µF(1)
and 10µF(1)
+
VCC
1
VCC
2
1
2
24
23
22
21
20
19
18
17
16
15
14
13
+
V
V
V
V
V
CC1
INR
AGND1
AGND2
VCOM
1µF
+
Rch In
Lch In
3
4.7µF(4)
+
4.7µF(2)
4.7µF(2)
+
+
REFL
REFR
INL
4
4.7µF(4)
+
Rch Out(5)
VOUT
R
5
1µF
+
4.7µF(4)
VOUTL
6
+
Lch Out(5)
MC(6)/DEM0(7)
RST/PDAD
ML/PDDA
SYSCLK
LRCIN
MC/DEM0
MD/DEM1
ZFLG/20BIT
DIN
7
MD(6)/DEM1(7)
8
ZFLG(6)/20BIT(7)
SYSCLK
9
L/R CLK
BIT CLK
10kΩ
10
11
12
Control
Interface
BCKIN
VDD
Audio
Interface
DOUT
DATA OUT
DGND
0.1µF
and
10µF(1)
DATA IN
ML(6)/PDDA(7)
RST(6)/PDAD(7)
NOTES: (1) 0.1µF ceramic and 10µF tantalum, typical, depending on power supply quality and
pattern layout. (2) 4.7µF typical, gives settling time with 30ms (4.7µF x 6.4kΩ) time constant in
Power ON and Power-Down OFF period. (3) 1µF typical, gives 5.3Hz cut-off frequency of input
HPF in normal operation and gives settling time with 30ms (1µF x 30kΩ) time constant in Power
ON and Power -Down OFF period. (4) 4.7µF typical, gives 3.4Hz cut-off frequency of output HPF
in normal operation and gives settling time with 47ms (4.7µF x 10kΩ) time constant in Power ON
and Power-Down OFF period. (5) Post low pass filter with RIN >10kΩ, depending on requirement
of system performance. (6) MC, MD, ML, ZFLG, RST and 10kΩ pull-up resistor are for the
PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.
FIGURE 12. Typical Connection Diagram for PCM3002/3003.
®
PCM3002/3003
20
BB [ BURR-BROWN CORPORATION ]
