PCM1808
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SLES177A–APRIL 2006–REVISED AUGUST 2006
INTERFACE TIMING
Figure 22 and Figure 23 illustrate the interface timing in slave mode and master mode, respectively.
t
(LRCP)
1.4 V
LRCK
t
t
(BCKL)
(LRSU)
t
(LRHD)
t
(BCKH)
1.4 V
BCK
t
t
(LRDO)
t
(CKDO)
(BCKP)
0.5 V
DD
DOUT
T0017-02
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
ns
t(BCKP)
BCK period
1/(64 fS)
1.5 × t(SCKI)
1.5 × t(SCKI)
50
t(BCKH)
t(BCKL)
t(LRSU)
t(LRHD)
t(LRCP)
t(CKDO)
t(LRDO)
tr
BCK pulse duration, HIGH
BCK pulse duration, LOW
LRCK setup time to BCK rising edge
LRCK hold time to BCK rising edge
LRCK period
ns
ns
ns
10
ns
10
µs
ns
Delay time, BCK falling edge to DOUT valid
Delay time, LRCK edge to DOUT valid
Rise time of all signals
–10
40
40
20
20
–10
ns
ns
tf
Fall time of all signals
ns
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rise and fall times are from 10% to
90% of the input/output signal swing. Load capacitance of DOUT is 20 pF. t(SCKI) is the SCKI period.
Figure 22. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs)
16
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