PCM1808
www.ti.com
SLES177A–APRIL 2006–REVISED AUGUST 2006
Fade-In Complete
Fade-In Start
Fade-Out Start
Fade-Out Complete
DOUT
(Contents)
BPZ
48/f or 48/f
48/f or 48/f
in
in
S
S
T0080-01
Figure 18. Fade-In and Fade-Out Operations
POWER ON
The PCM1808 has an internal power-on-reset circuit, and initialization (reset) is performed automatically when
the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts
after VDD > 2.2 V (typical), the PCM1808 stays in the reset state and the digital output is forced to zero. The
digital output is valid after the reset state is released and the time of 8960/fS has elapsed. Because the fade-in
operation is performed, it takes additional time of 48/fin or 48/fS until the data corresponding to the analog input
signal is obtained. Figure 19 illustrates the power-on timing and the digital output.
2.6 V
2.2 V
1.8 V
V
DD
Reset
Reset Release
Operation
Internal
Reset
1024 System Clocks
8960/f
S
System
Clock
DOUT
Zero Data
Normal Data
Fade-In Complete
Fade-In Start
DOUT
(Contents)
BPZ
48/f or 48/f
in
S
T0014-09
Figure 19. Power-On Timing
12
Submit Documentation Feedback
BB [ BURR-BROWN CORPORATION ]
