PCM1808
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SLES177A–APRIL 2006–REVISED AUGUST 2006
CLOCK-HALT POWER-DOWN AND RESET FUNCTION
The PCM1808 has a power-down and reset function, which is triggered by halting SCKI (pin 6) in both master
and slave modes. The function is available anytime after power on. Reset and power down are performed
automatically 4 µs (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1808 stays in
the reset and power-down mode, and DOUT (pin 9) is forced to zero. SCKI must be supplied to release the
reset and power-down mode. The digital output is valid after the reset state is released and the time of 1024
SCKI + 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or
48/fS until the level corresponding to the analog input signal is obtained. Figure 20 illustrates the clock-halt reset
timing.
To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKI
within 4480/fS after SCKI is resumed. If it takes more than 4480/fS for BCK and LRCK to synchronize with SCKI,
SCKI should be masked until the synchronization is achieved again, taking care of glitch and jitter. See the
typical circuit connection diagram, Figure 26.
To avoid ADC performance degradation, the clock-halt reset also should be asserted when system clock SCKIor
the audio interface clocks BCK and LRCK (sampling rate fS) are changed on the fly.
SCKI Halt
SCKI Resume
Fixed to Low or High
SCKI
t
Reset: t
(RST)
(CKR)
Clock-Halt Reset
Reset Release: t
(REL)
Internal
Reset
Operation
Operation
DOUT
Normal Data
Zero Data
Normal Data
Fade-In Complete
Fade-In Start
Normal Data
DOUT
(Contents)
BPZ
48/f or 48/f
in
S
T0081-01
SYMBOL
PARAMETER
MIN
MAX
UNIT
µs
t(CKR)
t(RST)
t(REL)
Delay time from SCKI halt to internal reset
Delay time from SCKI resume to reset release
Delay time from reset release to DOUT output
4
1024 SCKI
8960/fS
µs
µs
Figure 20. Clock-Halt Power-Down and Reset Timing
13
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