ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
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SBAS274E − MARCH 2003 − REVISED JUNE 2004
RESETTING THE ADS1605
RESETTING THE ADS1606
The ADS1605 and ADS1606 with FIFO disabled are
asynchronously reset when the RESET pin is taken low.
During reset, all of the digital circuits are cleared,
DOUT[15:0] are forced low, and DRDY forced high. It is
recommended that the RESET pin be released on the
falling edge of CLK. Afterwards, DRDY goes low on the
second rising edge of CLK. Allow 47 DRDY cycles for the
digital filter to settle before retrieving data. See Figure 3 for
the timing specifications.
The ADS1606 with the FIFO enabled requires a different
reset sequence than the ADS1605, as shown in Figure 16.
Ignore any DRDY toggles that occur while RESET is low.
Release RESET on the rising edge of CLK, then
afterwards toggle RD to complete the reset sequence.
CLK
Reset can be used to synchronize multiple ADS1605s. All
devices to be synchronized must use a common CLK
input. With the CLK inputs running, pulse RESET on the
falling edge of CLK, as shown in Figure 15. Afterwards, the
converters will be converting synchronously with the
RESET
Ignore
t26
DRDY
DRDY
outputs
updating
simultaneously.
After
synchronization, allow 47 DRDY cycles (t12) for output
data to fully settle.
R
D
Toggle RD to complete reset sequence
ADS16051
Figure 16. Resetting the ADS1606 with the FIFO
Enabled
RESET
Clock
RESET
CLK
DRDY
DRDY1
DOUT[15:0]
DOUT[15:0]1
After resetting, the settling time for the ADS1606 is 47 CLK
cycles, regardless of the FIFO level. Therefore, for higher
FIFO levels, it takes fewer DRDY cycles to settle because
the DRDY period is longer. Table 4 shows the number of
DRDY cycles required to settle for each FIFO level.
ADS16052
RESET
CLK
DRDY
DRDY2
DOUT[15:0]
DOUT[15:0]2
Table 4. ADS1606 Reset Settling
CLK
FILTER SETTLING TIME AFTER RESET
(t in units of DRDY cycles )
26
FIFO LEVEL
2
4
24
12
8
RESET
t12
DRDY1
6
8
6
Settled
Data
DOUT[15:0]1
10
12
14
5
4
4
DRDY2
Settled
Data
DOUT[15:0]2
Synchronized
Figure 15. Synchronizing Multiple Converters
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