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SBAS274E − MARCH 2003 − REVISED JUNE 2004
Likewise, when the input is negative out-of-range by going
below the negative full-scale value of –1.545VREF, the output
clips to 8000h and the OTR output goes high. The OTR
remains high while the input signal is out-of-range.
CLOCK INPUT (CLK)
The ADS1605/6 requires an external clock signal to be
applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with any
high-speed data converter, a high quality clock is essential
for optimum performance. Crystal clock oscillators are the
recommended CLK source; other sources, such as
frequency synthesizers are usually not adequate. Make
sure to avoid excess ringing on the CLK input; keeping the
trace as short as possible will help.
Table 2. Output Code Versus Input Signal
INPUT SIGNAL
(INP – INN)
IDEAL OUTPUT
(1)
CODE
OTR
≥+1.545V
(> 0dB)
7FFF
1
0
0
REF
H
H
1.545V
(0dB)
7FFF
0001
REF
Measuring high frequency, large amplitude signals
requires tight control of clock jitter. The uncertainty during
sampling of the input from clock jitter limits the maximum
achievable SNR. This effect becomes more pronounced
with higher frequency and larger magnitude inputs.
Fortunately, the ADS1605/6 oversampling topology
reduces clock jitter sensitivity over that of Nyquist rate
converters like pipeline and successive approximation
+1.545VREF
H
2
15 * 1
0
0000
0
0
H
FFFF
−1.545VREF
H
2
15 * 1
8000
0
1
215
H
ǒ
Ǔ
−1.545VREF
Ǹ
215 * 1
converters by a factor of 8.
8000
215
215 * 1
H
In order to not limit the ADS1605/6 SNR performance,
keep the jitter on the clock source below the values shown
in Table 1. When measuring lower frequency and lower
amplitude inputs, more CLK jitter can be tolerated. In
determining the allowable clock source jitter, select the
worst-case input (highest frequency, largest amplitude)
that will be seen in the application.
ǒ
Ǔ
v −1.545VREF
(1)
Excludes effects of noise, INL, offset and gain errors.
OUT-OF-RANGE INDICATION (OTR)
If the output code on DOUT[15:0] exceeds the positive or
negative full-scale, the out-of-range digital output OTR will
go high on the falling edge of DRDY. When the output code
returns within the full-scale range, OTR returns low on the
falling edge of DRDY.
Table 1. Maximum Allowable Clock Source Jitter
for Different Input Signal Frequencies and
Amplitude
MAXIMUM
ALLOWABLE
CLOCK SOURCE
JITTER
INPUT SIGNAL
DATA RETRIEVAL
Data retrieval is controlled through a simple parallel
interface. The falling edge of the DRDY output indicates
new data is available. To activate the output bus, both CS
and RD must be low, as shown in Table 3. Make sure the
DOUT bus does not drive heavy loads (> 20pF), as this will
degrade performance. Use an external buffer when driving
an edge connector or cables.
MAXIMUM
MAXIMUM
FREQUENCY
AMPLITUDE
2MHz
2MHz
−2dB
−20dB
−2dB
1.9ps
14ps
3.8ps
28ps
7.6ps
57ps
38ps
285ps
1MHz
1MHz
−20dB
−2dB
500kHz
500kHz
100kHz
100kHz
Table 3. Truth Table for CS and RD
−20dB
−2dB
CS
0
RD
0
DOUT[15:0]
Active
−20dB
0
1
High impedance
High impedance
High impedance
1
0
DATA FORMAT
1
1
The 16-bit output data is in binary two’s complement format
as shown in Table 2. When the input is positive out-of-range,
exceeding the positive full-scale value of 1.545VREF, the
output clips to all 7FFFh and the OTR output goes high.
20
BB [ BURR-BROWN CORPORATION ]
