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SBAS274E − MARCH 2003 − REVISED JUNE 2004
output code of 7FFFh. Likewise, the most negative
measurable differential input is –1.545VREF, which produces
the most negative digital output code of 8000h.
OVERVIEW
The ADS1605 and ADS1606 are high-performance
delta-sigma ADCs with a default oversampling ratio of 8. The
modulator uses an inherently stable 2-1-1 pipelined
delta-sigma modulator architecture incorporating proprietary
circuitry that allows for very linear high-speed operation. The
modulator samples the input signal at 40MSPS (when
fCLK = 40MHz). A low-ripple linear phase digital filter
decimates the modulator output to provide data output word
rates of 5MSPS with a signal passband out to 2.45MHz. The
2X mode, enabled by a digital I/O pin, doubles the data rate
to 10MSPS by reducing the oversampling ratio to 4. See the
2X Mode section for more details.
The ADS1605/6 supports a very wide range of input signals.
For VREF = 3V, the full scale input voltages are 4.6V. Having
such a wide input range makes out-of-range signals unlikely.
However, should an out-of-range signal occur, the digital
output OTR will go high.
To achieve the highest analog performance, it is
recommended that the inputs be limited to 1.227VREF
(−2dBFS). For VREF = 3V, the corresponding recommended
input range is 3.68V.
The analog inputs must be driven with a differential signal to
achieve optimum performance. The recommended
Conceptually, the modulator and digital filter measure the dif-
ferential input signal, VIN = (AINP – AINN), against the scaled
differential reference, VREF = (VREFP – VREFN), as shown
in Figure 7. The voltage reference can either be generated
internally or supplied externally. An 16-bit parallel data bus,
designed for direct connection to DSPs, outputs the data. A
separate power supply for the I/O allows flexibility for interfac-
ing to different logic families. Out-of-range conditions are indi-
cated with a dedicated digital output pin. Analog power dis-
sipation is controlled using an external resistor. This allows
reduced dissipation when operating at slower speeds. When
not in use, power consumption can be dramatically reduced
using the PD pin.
common-mode
voltage
of
the
input
signal,
AINP ) AINN
VCM
+
, is 2.0V. For signals larger than
2
−2dBFS, the input common-mode voltage needs to be raised
in order to meet the absolute input voltage specifications. The
typical characteristics show how performance varies with
input common-mode voltage.
In addition to the differential and common-mode input
voltages, the absolute input voltage is also important. This is
the voltage on either input (AINP or AINN) with respect to
AGND. The range for this voltage is:
* 0.1V t (AINN or AINP) t 4.6V
The ADS1606 incorporates an adjustable FIFO buffer for the
output data. The level of the FIFO is set by the
FIFO_LEV[2:0] pins. Other than the FIFO buffer, the
ADS1605 and ADS1606 are identical, and are referred to to-
gether in this data sheet as the ADS1605/6.
If either input is taken below –0.1V, ESD protection diodes on
the inputs will turn on. Exceeding 4.6V on either input will
result in degradation in the linearity performance. ESD
protection diodes will also turn on if the inputs are taken
above AVDD (+5V).
ANALOG INPUTS (AINP, AINN)
For signals below –2dBFS, the recommended absolute input
voltage is:
The ADS1605/6 measures the differential signal,
VIN = (AINP − AINN), against the differential reference,
VREF = (VREFP – VREFN). The reference is scaled
internally so that the full-scale differential input voltage is
1.545VREF. That is, the most positive measurable differential
input is 1.545VREF, which produces the most positive digital
* 0.1V t (AINN or AINP) t 4.2V
Keeping the inputs within this range provides for optimum
performance.
VREFP VREFN
IOVDD
Σ
VREF
1.545
OTR
1.545VREF
Digital
ADS1606 Only
Parallel
Interface
DOUT[15:0]
FIFO
VIN
AINP
AINN
Σ∆
Modulator
Filter
Σ
FIFO_LEV[2:0]
2XMODE
Figure 7. Conceptual Block Diagram
17
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