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ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
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SBAS274E − MARCH 2003 − REVISED JUNE 2004
32/fCLK
128/fCLK
DRDY
RD
Figure 24. Example of Skipping Readback when FIFO Level = 4
32/fCLK
64/fCLK
DRDY
RD
FIFO_LEV[2:0]
010 (Level = 4)
100 (Level = 8)
Change FIFO_LEV[2:0] here
Figure 25. Example of Synchronized Change of FIFO Level from 4 to 8
ANALOG POWER DISSIPATION
Table 6. Recommended R
Resistor Values for
BIAS
Different CLK Frequencies
An external resistor connected between the RBIAS pin and
the analog ground sets the analog current level, as shown in
Figure 26. The current is inversely proportional to the resistor
value. Table 6 shows the recommended values of RBIAS for
different CLK frequencies. Notice that the analog current can
be reduced when using a slower frequency CLK input
because the modulator has more time to settle. Avoid adding
any capacitance in parallel to RBIAS , since this will interfere
with the internal circuitry used to set the biasing.
TYPICAL POWER
DISSIPATION WITH REFEN
HIGH
DATA
RATE
f
R
BIAS
CLK
16MHz
24MHz
32MHz
40MHz
2MHz
3MHz
4MHz
5MHz
60kΩ
50kΩ
45kΩ
37kΩ
315mW
400mW
475mW
570mW
POWER DOWN (PD)
ADS1605
ADS1606
When not in use, the ADS1605/6 can be powered down by
taking the PD pin low. All circuitry will be shutdown,
including the voltage reference. To minimize the digital
current during power down, stop the clock signal supplied
to the CLK input. There is an internal pull-up resistor of
170kΩ on the PD pin, but it is recommended that this pin
be connected to IOVDD if not used. If using the ADS1606
with the FIFO enabled, issue a reset after exiting
power-down mode. Make sure to allow time for the
reference to start up after exiting power-down mode. The
internal reference typically requires 15ms. After the
reference has stabilized, allow at least 100 DRDY cycles
for the modulator and digital filter to settle before retrieving
data.
RBIAS
RBIAS
AGND
Figure 26. External Resistor Used to Set Analog
Power Dissipation
25
BB [ BURR-BROWN CORPORATION ]
