ꢐ ꢕꢙ ꢚꢋ ꢛꢛ
ꢐ ꢕꢙ ꢚꢋ ꢛꢜ
www.ti.com
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
DATA FORMAT
CLOCK OUTPUT (D0/CLKOUT)
The ADS1255/6 output 24 bits of data in Binary Two’s
The clock output pin can be used to clock another device,
such as a microcontroller. This clock can be configured to
operate at frequencies of fCLKIN, fCLKIN/2, or fCLKIN/4 using
CLK1 and CLK0 in the ADCON register. Note that enabling
the output clock and driving an external load will increase
the digital power dissipation. Standby mode does not
affect the clock output status. That is, if Standby is
enabled, the clock output will continue to run during
Standby mode. If the clock output function is not needed,
it should be disabled by writing to the ADCON register after
power-up or reset.
Complement format. The LSB has
a weight of
2VREF/(PGA(223 − 1)). A positive full-scale input produces
an output code of 7FFFFFh and the negative full-scale
input produces an output code of 800000h. The output
clips at these codes for signals exceeding full-scale.
Table 16 summarizes the ideal output codes for different
input signals.
Table 16. Ideal Output Code vs Input Signal
INPUT SIGNAL V
IN
(1)
IDEAL OUTPUT CODE
(AIN − AIN )
P
N
CLOCK GENERATION
) 2VREF
7FFFFFh
The master clock source for the ADS1255/6 can be
provided using an external crystal or clock generator.
When the clock is generated using a crystal, external
capacitors must be provided to ensure start-up and a
stable clock frequency, as shown in Figure 22. Table 17
lists two recommended crystals. Long leads should be
minimized with the crystal placed close to the ADS1255/6
pins. For information on ceramic resonators, see
application note SBAA104, Using Ceramic Resonators
with the ADS1255/6, available for download at
www.ti.com.
w
PGA
) 2VREF
000001h
000000h
FFFFFFh
23
(
)
PGA 2 * 1
0
* 2VREF
23
(
)
PGA 2 * 1
* 2VREF
223
223 * 1
800000h
ǒ
Ǔ
v
PGA
(1)
Excludes effects of noise, INL, offset, and gain errors.
XTAL1/CLKIN
C1
GENERAL-PURPOSE DIGITAL I/O (D0-D3)
Crystal
The ADS1256 has 4 pins dedicated for digital I/O and the
ADS1255 has 2 digital I/O pins. All of the digital I/O pins are
individually configurable as either inputs or outputs
through the IO register. The DIR bits of the IO register
define whether each pin is an input or output, and the DIO
bits control the status of the pins. Reading back the DIO
register shows the state of the digital I/O pins, whether they
are configured as inputs or outputs by the DIR bits. When
digital I/O pins are configured as inputs, the DIO register
is used to read the state of these pins. When configured as
outputs, DIO sets the output value. On the ADS1255, the
digital I/O pins D2 and D3 do not exist and the settings of
the IO register bits that control operation of D2 and D3
have no effect on that device.
XTAL2
C2
C1, C2: 5pF to 20pF
Figure 22. Crystal Connection
Table 17. Recommended Crystals
PART
NUMBER
MANUFACTURER
FREQUENCY
Citizen
ECS
7.68MHz
8.0MHz
CIA/53383
ECS-80-5-4
During Standby and Power-Down modes, the GPIO
remain active. If configured as outputs, they continue to
drive the pins. If configured as inputs, they must be driven
(not left floating) to prevent excess power dissipation.
When using a crystal, neither the XTAL1/CLKIN nor
XTAL2 pins can be used to drive any other logic. If other
devices need a clock source, the D0/CLKOUT pin is
available for this function. When using an external clock
generator, supply the clock signal to XTAL1/CLKIN and
leave XTAL2 floating. Make sure the external clock
generator supplies a clean clock waveform. Overshoot
and glitches on the clock will degrade overall performance.
The digital I/O pins are set as inputs after power-up or a
reset, except for D0/CLKOUT, which is enabled as a clock
output. If the digital I/O pins are not used, either leave them
as inputs tied to ground or configure them as outputs. This
prevents excess power dissipation.
23
BB [ BURR-BROWN CORPORATION ]
